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fd79485dfa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187349 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s
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; This test checks that the VMLxForwarting feature is disabled for A15.
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; CHECK: fun_a:
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define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{
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%1 = add <4 x i32> %x, %y
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; CHECK-NOT: vmul
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; CHECK: vmla
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%2 = mul <4 x i32> %1, %1
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%3 = add <4 x i32> %y, %2
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ret <4 x i32> %3
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}
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; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting
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; Cortex-A15.
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; CHECK: fun_b:
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define <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{
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; CHECK: vmla.f32
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%t = fmul <4 x float> %x, %y
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%r = fadd <4 x float> %t, %z
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ret <4 x float> %r
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}
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; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition
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; operations when targeting Cortex-A15.
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; CHECK: fun_c:
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define <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{
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; CHECK: vmla.f32
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%t1 = fmul <4 x float> %x, %y
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%r1 = fadd <4 x float> %t1, %z
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; CHECK: vmla.f32
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%t2 = fmul <4 x float> %u, %v
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%r2 = fadd <4 x float> %t2, %r1
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ret <4 x float> %r2
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}
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