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0ff4287fe2
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target triple = "nvptx-nvidia-cuda"
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; Function Attrs: nounwind
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; CHECK: .entry foo
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define void @foo(float* nocapture %a) #0 {
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%val = load float* %a
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%tan = tail call fastcc float @__nv_fast_tanf(float %val)
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store float %tan, float* %a
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.nvvm.sin.approx.ftz.f(float) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.nvvm.cos.approx.ftz.f(float) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.nvvm.div.approx.ftz.f(float, float) #1
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; Function Attrs: alwaysinline inlinehint nounwind readnone
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; CHECK: .func (.param .b32 func_retval0) __nv_fast_tanf
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define internal fastcc float @__nv_fast_tanf(float %a) #2 {
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entry:
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%0 = tail call float @llvm.nvvm.sin.approx.ftz.f(float %a)
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%1 = tail call float @llvm.nvvm.cos.approx.ftz.f(float %a)
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%2 = tail call float @llvm.nvvm.div.approx.ftz.f(float %0, float %1)
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ret float %2
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { alwaysinline inlinehint nounwind readnone }
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!nvvm.annotations = !{!0}
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!0 = metadata !{void (float*)* @foo, metadata !"kernel", i32 1}
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