mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-30 16:17:05 +00:00
827b7a070d
The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
428 B
LLVM
15 lines
428 B
LLVM
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
|
target triple = "powerpc64-bgq-linux"
|
|
; RUN: llc < %s -march=ppc64 -mcpu=a2 | FileCheck %s
|
|
|
|
define i32 @zytest(i32 %a) nounwind {
|
|
entry:
|
|
; CHECK: @zytest
|
|
%r = call i32 asm "lwbrx $0, ${1:y}", "=r,Z"(i32 %a) nounwind, !srcloc !0
|
|
ret i32 %r
|
|
; CHECK: lwbrx 3, 0,
|
|
}
|
|
|
|
!0 = metadata !{i32 101688}
|
|
|