llvm-6502/test/CodeGen/PowerPC/ppc64-zext.ll at f89f66e61b26974bb73b5832d5825091873b51dc - llvm-6502 - Applefritter: Git

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Hal Finkel 97d047dec7 Optimize zext on PPC64.

The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8

2012-08-28 02:10:15 +00:00

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 ; RUN: llc < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux"
 define i64 @fun(i32 %arg32) nounwind {
 entry:
 ; CHECK: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 32
   %o = zext i32 %arg32 to i64
   ret i64 %o
 }