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e2ff00e117
We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186108 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
992 B
LLVM
19 lines
992 B
LLVM
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
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target triple = "powerpc64-unknown-linux-gnu"
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define void @autogen_SD367951() {
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BB:
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%Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24>
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%Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18>
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%Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer
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%E27 = extractelement <16 x i1> %Cmp11, i32 5
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br label %CF76
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CF76: ; preds = %CF80, %CF76, %BB
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br i1 undef, label %CF76, label %CF80
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CF80: ; preds = %CF76
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%Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff
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br label %CF76
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}
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