mirror of
				https://github.com/c64scene-ar/llvm-6502.git
				synced 2025-10-31 08:16:47 +00:00 
			
		
		
		
	Try to use MVC when spilling the destination of a simple load or the source
of a simple store.  As explained in the comment, this doesn't yet handle
the case where the load or store location is also a frame index, since
that could lead to two simultaneous scavenger spills, something the
backend can't handle yet.  spill-02.py tests that this restriction kicks in,
but unfortunately I've not yet found a case that would fail without it.
The volatile trick I used for other scavenger tests doesn't work here
because we can't use MVC for volatile accesses anyway.
I'm planning on relaxing the restriction later, hopefully with a test
that does trigger the problem...
Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly
classified as SimpleBDX{Load,Store}.  It wouldn't be easy to test for
that bug separately, which is why I didn't split out the fix as a
separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434 91177308-0d34-0410-b5e6-96231b3b80d8
		
	
		
			
				
	
	
		
			41 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			Python
		
	
	
	
	
	
			
		
		
	
	
			41 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			Python
		
	
	
	
	
	
| # Test cases where MVC is used for spill slots that end up being out of range.
 | |
| # RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
 | |
| 
 | |
| # There are 8 usable call-saved GPRs, two of which are needed for the base
 | |
| # registers.  The first 160 bytes of the frame are needed for the ABI
 | |
| # call frame, and a further 8 bytes are needed for the emergency spill slot.
 | |
| # That means we will have at least one out-of-range slot if:
 | |
| #
 | |
| #    count == (4096 - 168) / 8 + 6 + 1 == 498
 | |
| #
 | |
| # Add in some extra room and check both %r15+4096 (the first out-of-range slot)
 | |
| # and %r15+4104.
 | |
| #
 | |
| # CHECK: f1:
 | |
| # CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
 | |
| # CHECK: mvc 0(8,[[REG]]), {{[0-9]+}}({{%r[0-9]+}})
 | |
| # CHECK: brasl %r14, foo@PLT
 | |
| # CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
 | |
| # CHECK: mvc {{[0-9]+}}(8,{{%r[0-9]+}}), 8([[REG]])
 | |
| # CHECK: br %r14
 | |
| count = 500
 | |
| 
 | |
| print 'declare void @foo()'
 | |
| print ''
 | |
| print 'define void @f1(i64 *%base0, i64 *%base1) {'
 | |
| 
 | |
| for i in range(count):
 | |
|     print '  %%ptr%d = getelementptr i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
 | |
|     print '  %%val%d = load i64 *%%ptr%d' % (i, i)
 | |
|     print ''
 | |
| 
 | |
| print '  call void @foo()'
 | |
| print ''
 | |
| 
 | |
| for i in range(count):
 | |
|     print '  store i64 %%val%d, i64 *%%ptr%d' % (i, i)
 | |
| 
 | |
| print ''
 | |
| print '  ret void'
 | |
| print '}'
 |