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https://github.com/c64scene-ar/llvm-6502.git
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b12c642bbf
gcc inline asm supports specifying "cc" as a clobber of all condition registers. Add just enough modeling of the full register to make this work. Fixed PR19326. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205630 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
1.4 KiB
LLVM
71 lines
1.4 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i64 @test1(i64 %a, i64 %b) {
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entry:
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%c = icmp eq i64 %a, %b
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br label %foo
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foo:
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call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)
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br i1 %c, label %bar, label %end
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bar:
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ret i64 %b
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end:
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ret i64 %a
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; CHECK-LABEL: @test1
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; CHECK: mfcr [[REG1:[0-9]+]]
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; CHECK-DAG: cmpd
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; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
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; CHECK-DAG: stw [[REG1]], 8(1)
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; CHECK-DAG: stw [[REG2]], -4(1)
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; CHECK: sc
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; CHECK: lwz [[REG3:[0-9]+]], -4(1)
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; CHECK: mtocrf 128, [[REG3]]
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; CHECK: lwz [[REG4:[0-9]+]], 8(1)
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; CHECK-DAG: mtocrf 32, [[REG4]]
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; CHECK-DAG: mtocrf 16, [[REG4]]
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; CHECK-DAG: mtocrf 8, [[REG4]]
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; CHECK: blr
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}
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define i64 @test2(i64 %a, i64 %b) {
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entry:
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%c = icmp eq i64 %a, %b
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br label %foo
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foo:
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call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a)
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br i1 %c, label %bar, label %end
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bar:
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ret i64 %b
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end:
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ret i64 %a
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; CHECK-LABEL: @test2
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; CHECK: mfcr [[REG1:[0-9]+]]
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; CHECK-DAG: cmpd
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; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
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; CHECK-DAG: stw [[REG1]], 8(1)
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; CHECK-DAG: stw [[REG2]], -4(1)
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; CHECK: sc
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; CHECK: lwz [[REG3:[0-9]+]], -4(1)
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; CHECK: mtocrf 128, [[REG3]]
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; CHECK: lwz [[REG4:[0-9]+]], 8(1)
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; CHECK-DAG: mtocrf 32, [[REG4]]
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; CHECK-DAG: mtocrf 16, [[REG4]]
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; CHECK-DAG: mtocrf 8, [[REG4]]
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; CHECK: blr
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}
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