mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
7a5d9c0611
hard coded command line option for the Mips soft float tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236801 91177308-0d34-0410-b5e6-96231b3b80d8
241 lines
6.8 KiB
LLVM
241 lines
6.8 KiB
LLVM
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci
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@i = global i32 0, align 4
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@j = common global i32 0, align 4
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@k = common global i32 0, align 4
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; Function Attrs: nounwind optsize
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define i32 @x0() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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tail call void asm sideeffect ".space 1000", ""() #1, !srcloc !5
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br label %if.end
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if.else: ; preds = %entry
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tail call void asm sideeffect ".space 1004", ""() #1, !srcloc !6
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%storemerge = phi i32 [ 1, %if.else ], [ 0, %if.then ]
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store i32 %storemerge, i32* @i, align 4, !tbaa !1
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ret i32 0
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}
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; ci: .ent x0
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; ci: beqz $3, $BB0_2
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; ci: $BB0_2:
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; ci: .end x0
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; Function Attrs: nounwind optsize
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define i32 @x1() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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tail call void asm sideeffect ".space 1000000", ""() #1, !srcloc !7
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br label %if.end
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if.else: ; preds = %entry
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tail call void asm sideeffect ".space 1000004", ""() #1, !srcloc !8
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%storemerge = phi i32 [ 1, %if.else ], [ 0, %if.then ]
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store i32 %storemerge, i32* @i, align 4, !tbaa !1
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ret i32 0
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}
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; ci: .ent x1
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; ci: bnez $3, $BB1_1 # 16 bit inst
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; ci: jal $BB1_2 # branch
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; ci: nop
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; ci: $BB1_1:
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; ci: .end x1
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; Function Attrs: nounwind optsize
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define i32 @y0() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 10, i32* @j, align 4, !tbaa !1
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tail call void asm sideeffect ".space 1000", ""() #1, !srcloc !9
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br label %if.end
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if.else: ; preds = %entry
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store i32 55, i32* @j, align 4, !tbaa !1
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tail call void asm sideeffect ".space 1004", ""() #1, !srcloc !10
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret i32 0
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}
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; ci: .ent y0
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; ci: beqz $2, $BB2_2
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; ci: .end y0
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; Function Attrs: nounwind optsize
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define i32 @y1() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 10, i32* @j, align 4, !tbaa !1
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tail call void asm sideeffect ".space 1000000", ""() #1, !srcloc !11
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br label %if.end
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if.else: ; preds = %entry
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store i32 55, i32* @j, align 4, !tbaa !1
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tail call void asm sideeffect ".space 1000004", ""() #1, !srcloc !12
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret i32 0
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}
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; ci: .ent y1
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; ci: bnez $2, $BB3_1 # 16 bit inst
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; ci: jal $BB3_2 # branch
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; ci: nop
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; ci: $BB3_1:
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; ci: .end y1
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; Function Attrs: nounwind optsize
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define void @z0() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%1 = load i32, i32* @j, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, %1
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32* @k, align 4, !tbaa !1
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tail call void asm sideeffect ".space 10000", ""() #1, !srcloc !13
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br label %if.end
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if.else: ; preds = %entry
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tail call void asm sideeffect ".space 10004", ""() #1, !srcloc !14
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store i32 2, i32* @k, align 4, !tbaa !1
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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; ci: .ent z0
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; ci: btnez $BB4_2
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; ci: .end z0
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; Function Attrs: nounwind optsize
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define void @z1() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%1 = load i32, i32* @j, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, %1
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32* @k, align 4, !tbaa !1
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tail call void asm sideeffect ".space 10000000", ""() #1, !srcloc !15
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br label %if.end
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if.else: ; preds = %entry
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tail call void asm sideeffect ".space 10000004", ""() #1, !srcloc !16
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store i32 2, i32* @k, align 4, !tbaa !1
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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; ci: .ent z1
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; ci: bteqz $BB5_1 # 16 bit inst
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; ci: jal $BB5_2 # branch
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; ci: nop
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; ci: $BB5_1:
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; ci: .end z1
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; Function Attrs: nounwind optsize
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define void @z3() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%1 = load i32, i32* @j, align 4, !tbaa !1
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%cmp1 = icmp sgt i32 %0, %1
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %entry, %if.then
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tail call void asm sideeffect ".space 10000", ""() #1, !srcloc !17
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%2 = load i32, i32* @i, align 4, !tbaa !1
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%3 = load i32, i32* @j, align 4, !tbaa !1
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%cmp = icmp sgt i32 %2, %3
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br i1 %cmp, label %if.then, label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; ci: .ent z3
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; ci: bteqz $BB6_2
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; ci: .end z3
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; Function Attrs: nounwind optsize
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define void @z4() #0 {
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entry:
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%0 = load i32, i32* @i, align 4, !tbaa !1
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%1 = load i32, i32* @j, align 4, !tbaa !1
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%cmp1 = icmp sgt i32 %0, %1
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %entry, %if.then
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tail call void asm sideeffect ".space 10000000", ""() #1, !srcloc !18
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%2 = load i32, i32* @i, align 4, !tbaa !1
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%3 = load i32, i32* @j, align 4, !tbaa !1
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%cmp = icmp sgt i32 %2, %3
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br i1 %cmp, label %if.then, label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; ci: .ent z4
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; ci: btnez $BB7_1 # 16 bit inst
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; ci: jal $BB7_2 # branch
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; ci: nop
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; ci: .align 2
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; ci: $BB7_1:
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; ci: .end z4
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{i32 57}
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!6 = !{i32 107}
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!7 = !{i32 188}
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!8 = !{i32 241}
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!9 = !{i32 338}
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!10 = !{i32 391}
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!11 = !{i32 477}
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!12 = !{i32 533}
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!13 = !{i32 621}
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!14 = !{i32 663}
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!15 = !{i32 747}
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!16 = !{i32 792}
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!17 = !{i32 867}
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!18 = !{i32 953}
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