mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-04 05:17:07 +00:00
c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.2 KiB
LLVM
71 lines
2.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
|
|
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
|
|
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
|
|
|
|
; FUNC-LABEL: {{^}}fneg_f32:
|
|
; R600: -PV
|
|
|
|
; GCN: v_xor_b32
|
|
define void @fneg_f32(float addrspace(1)* %out, float %in) {
|
|
%fneg = fsub float -0.000000e+00, %in
|
|
store float %fneg, float addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fneg_v2f32:
|
|
; R600: -PV
|
|
; R600: -PV
|
|
|
|
; GCN: v_xor_b32
|
|
; GCN: v_xor_b32
|
|
define void @fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
|
|
%fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
|
|
store <2 x float> %fneg, <2 x float> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fneg_v4f32:
|
|
; R600: -PV
|
|
; R600: -T
|
|
; R600: -PV
|
|
; R600: -PV
|
|
|
|
; GCN: v_xor_b32
|
|
; GCN: v_xor_b32
|
|
; GCN: v_xor_b32
|
|
; GCN: v_xor_b32
|
|
define void @fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
|
|
%fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
|
|
store <4 x float> %fneg, <4 x float> addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; DAGCombiner will transform:
|
|
; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
|
|
; unless the target returns true for isNegFree()
|
|
|
|
; FUNC-LABEL: {{^}}fneg_free_f32:
|
|
; R600-NOT: XOR
|
|
; R600: -KC0[2].Z
|
|
|
|
; XXX: We could use v_add_f32_e64 with the negate bit here instead.
|
|
; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
|
|
define void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
|
|
%bc = bitcast i32 %in to float
|
|
%fsub = fsub float 0.0, %bc
|
|
store float %fsub, float addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}fneg_fold_f32:
|
|
; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
|
|
; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
|
|
; GCN-NOT: xor
|
|
; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
|
|
define void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
|
|
%fsub = fsub float -0.0, %in
|
|
%fmul = fmul float %fsub, %in
|
|
store float %fmul, float addrspace(1)* %out
|
|
ret void
|
|
}
|