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80a3301b37
...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
2.1 KiB
LLVM
92 lines
2.1 KiB
LLVM
; Test compound shifts.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test a shift right followed by a sign extension. This can use two shifts.
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define i64 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
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; CHECK: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%shr = lshr i32 %a, 1
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%trunc = trunc i32 %shr to i1
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%ext = sext i1 %trunc to i64
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ret i64 %ext
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}
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; ...and again with the highest shift count that doesn't reduce to an
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; ashr/sext pair.
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define i64 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: sllg [[REG:%r[0-5]]], %r2, 33
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; CHECK: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%shr = lshr i32 %a, 30
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%trunc = trunc i32 %shr to i1
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%ext = sext i1 %trunc to i64
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ret i64 %ext
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}
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; Test a left shift that of an extended right shift in a case where folding
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; is possible.
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define i64 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK: risbg %r2, %r2, 27, 181, 9
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; CHECK: br %r14
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%shr = lshr i32 %a, 1
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 10
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%and = and i64 %shl, 137438952960
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ret i64 %and
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}
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; ...and again with a larger right shift.
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define i64 @f4(i32 %a) {
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; CHECK-LABEL: f4:
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; CHECK: risbg %r2, %r2, 30, 158, 3
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; CHECK: br %r14
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%shr = lshr i32 %a, 30
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%ext = sext i32 %shr to i64
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%shl = shl i64 %ext, 33
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%and = and i64 %shl, 8589934592
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ret i64 %and
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}
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; Repeat the previous test in a case where all bits outside the
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; bottom 3 matter.
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define i64 @f5(i32 %a) {
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; CHECK-LABEL: f5:
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; CHECK: risbg %r2, %r2, 29, 158, 3
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; CHECK: lhi %r2, 7
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; CHECK: br %r14
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%shr = lshr i32 %a, 30
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%ext = sext i32 %shr to i64
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%shl = shl i64 %ext, 33
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%or = or i64 %shl, 7
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ret i64 %or
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}
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; Test that SRA gets replaced with SRL if the sign bit is the only one
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; that matters.
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define i64 @f6(i64 %a) {
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; CHECK-LABEL: f6:
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; CHECK: risbg %r2, %r2, 55, 183, 19
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; CHECK: br %r14
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%shl = shl i64 %a, 10
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%shr = ashr i64 %shl, 60
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%and = and i64 %shr, 256
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ret i64 %and
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}
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; Test another form of f1.
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define i64 @f7(i32 %a) {
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; CHECK-LABEL: f7:
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; CHECK: sllg [[REG:%r[0-5]]], %r2, 62
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; CHECK: srag %r2, [[REG]], 63
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; CHECK: br %r14
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%1 = shl i32 %a, 30
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%sext = ashr i32 %1, 31
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%ext = sext i32 %sext to i64
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ret i64 %ext
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}
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