mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-04 05:17:07 +00:00
d47cb57ab8
This patch renames method 'isConstantSplat' as 'getConstantSplatValue' (mainly for consistency reasons), and rewrites its logic to ensure that we always perform a legal 'cast<ConstantSDNode>'. Added test shift-combine-crash.ll to verify that DAGCombiner no longer crashes with an assertion failure in the attempt to simplify a vector shift by a vector of all undef counts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204536 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.7 KiB
LLVM
58 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null
|
|
|
|
; Verify that DAGCombiner doesn't crash with an assertion failure in the
|
|
; attempt to cast a ISD::UNDEF node to a ConstantSDNode.
|
|
|
|
; During type legalization, the vector shift operation in function @test1 is
|
|
; split into two legal shifts that work on <2 x i64> elements.
|
|
; The first shift of the legalized sequence would be a shift by all undefs.
|
|
; DAGCombiner will then try to simplify the vector shift and check if the
|
|
; vector of shift counts is a splat. Make sure that llc doesn't crash
|
|
; at that stage.
|
|
|
|
|
|
define <4 x i64> @test1(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 1, i64 2>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
; Also, verify that DAGCombiner doesn't crash when trying to combine shifts
|
|
; with different combinations of undef elements in the vector shift count.
|
|
|
|
define <4 x i64> @test2(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 2, i64 3, i64 undef, i64 undef>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
define <4 x i64> @test3(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 3, i64 undef>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
define <4 x i64> @test4(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 undef, i64 2, i64 undef, i64 3>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
define <4 x i64> @test5(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 undef, i64 undef>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
define <4 x i64> @test6(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 3, i64 undef>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
define <4 x i64> @test7(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 3>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
define <4 x i64> @test8(<4 x i64> %A) {
|
|
%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 undef>
|
|
ret <4 x i64> %shl
|
|
}
|
|
|
|
|