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https://github.com/c64scene-ar/llvm-6502.git
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7c038bc15f
We were previously doing a post-order traversal and operating on the list in reverse, however this would occasionaly cause backedges for loops to be visited before some of the other blocks in the loop. We know use a reverse post-order traversal, which avoids this issue. The reverse post-order traversal is not completely ideal, so we need to manually fixup the list to ensure that inner loop backedges are visited before outer loop backedges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228186 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.5 KiB
LLVM
80 lines
2.5 KiB
LLVM
; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
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define void @main(float addrspace(1)* %out) {
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; CHECK: main_body:
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; CHECK: br label %LOOP.outer
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main_body:
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br label %LOOP.outer
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; CHECK: LOOP.outer:
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; CHECK: br label %LOOP
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LOOP.outer: ; preds = %ENDIF28, %main_body
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%temp8.0.ph = phi float [ 0.000000e+00, %main_body ], [ %tmp35, %ENDIF28 ]
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%temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ]
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br label %LOOP
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; CHECK: LOOP:
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; br i1 %{{[0-9]+}}, label %ENDIF, label %Flow
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LOOP: ; preds = %IF29, %LOOP.outer
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%temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ]
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%tmp20 = add i32 %temp4.0, 1
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%tmp22 = icmp sgt i32 %tmp20, 3
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br i1 %tmp22, label %ENDLOOP, label %ENDIF
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; CHECK: Flow3
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; CHECK: br i1 %{{[0-9]+}}, label %ENDLOOP, label %LOOP.outer
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; CHECK: ENDLOOP:
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; CHECK: ret void
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ENDLOOP: ; preds = %ENDIF28, %IF29, %LOOP
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%temp8.1 = phi float [ %temp8.0.ph, %LOOP ], [ %temp8.0.ph, %IF29 ], [ %tmp35, %ENDIF28 ]
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%tmp23 = icmp eq i32 %tmp20, 3
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%.45 = select i1 %tmp23, float 0.000000e+00, float 1.000000e+00
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store float %.45, float addrspace(1)* %out
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ret void
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; CHECK: ENDIF:
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; CHECK: br i1 %tmp31, label %IF29, label %Flow1
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ENDIF: ; preds = %LOOP
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%tmp31 = icmp sgt i32 %tmp20, 1
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br i1 %tmp31, label %IF29, label %ENDIF28
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; CHECK: Flow:
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; CHECK br i1 %{{[0-9]+}}, label %Flow, label %LOOP
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; CHECK: IF29:
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; CHECK: br label %Flow1
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IF29: ; preds = %ENDIF
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%tmp32 = icmp sgt i32 %tmp20, 2
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br i1 %tmp32, label %ENDLOOP, label %LOOP
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; CHECK: Flow1:
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; CHECK: br label %Flow
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; CHECK: Flow2:
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; CHECK: br i1 %{{[0-9]+}}, label %ENDIF28, label %Flow3
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; CHECK: ENDIF28:
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; CHECK: br label %Flow3
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ENDIF28: ; preds = %ENDIF
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%tmp35 = fadd float %temp8.0.ph, 1.0
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%tmp36 = icmp sgt i32 %tmp20, 2
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br i1 %tmp36, label %ENDLOOP, label %LOOP.outer
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}
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1
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; Function Attrs: readnone
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declare float @llvm.AMDIL.clamp.(float, float, float) #2
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { readnone }
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!0 = !{!1, !1, i64 0, i32 1}
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!1 = !{!"const", null}
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