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https://github.com/c64scene-ar/llvm-6502.git
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7373abd81e
Use CHECK-DAG to make these regression tests more resilient against changes in instruction scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195978 91177308-0d34-0410-b5e6-96231b3b80d8
161 lines
5.0 KiB
LLVM
161 lines
5.0 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-NOAV %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.__jmp_buf_tag = type { [64 x i64], i32, %struct.__sigset_t, [8 x i8] }
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%struct.__sigset_t = type { [16 x i64] }
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@env_sigill = internal global [1 x %struct.__jmp_buf_tag] zeroinitializer, align 16
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define void @foo() #0 {
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entry:
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call void @llvm.eh.sjlj.longjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
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unreachable
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; CHECK: @foo
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; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
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; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l
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; CHECK: ld 31, 0([[REG]])
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; CHECK: ld [[REG2:[0-9]+]], 8([[REG]])
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; CHECK: ld 1, 16([[REG]])
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; CHECK: mtctr [[REG2]]
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; CHECK: ld 30, 32([[REG]])
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; CHECK: ld 2, 24([[REG]])
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; CHECK: bctr
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return: ; No predecessors!
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ret void
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}
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declare void @llvm.eh.sjlj.longjmp(i8*) #1
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define signext i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = call i8* @llvm.frameaddress(i32 0)
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store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**)
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%1 = call i8* @llvm.stacksave()
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store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
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%2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
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%tobool = icmp ne i32 %2, 0
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br i1 %tobool, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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if.else: ; preds = %entry
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call void @foo()
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br label %if.end
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if.end: ; preds = %if.else
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store i32 0, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%3 = load i32* %retval
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ret i32 %3
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; FIXME: We should be saving VRSAVE on Darwin, but we're not!
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; CHECK: @main
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; CHECK: std
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; Make sure that we're not saving VRSAVE on non-Darwin:
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; CHECK-NOT: mfspr
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; CHECK-DAG: stfd
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; CHECK-DAG: stvx
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; CHECK-DAG: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
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; CHECK-DAG: std 31, env_sigill@toc@l([[REG]])
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; CHECK-DAG: addi [[REGA:[0-9]+]], [[REG]], env_sigill@toc@l
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; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
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; CHECK-DAG: std 1, 16([[REGA]])
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; CHECK-DAG: std 2, 24([[REGA]])
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; CHECK: bcl 20, 31, .LBB1_1
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; CHECK: li 3, 1
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; CHECK: #EH_SjLj_Setup .LBB1_1
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; CHECK: b .LBB1_2
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; CHECK: .LBB1_1:
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; CHECK: mflr [[REGL:[0-9]+]]
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; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload
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; CHECK: std [[REGL]], 8([[REG2]])
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; CHECK: li 3, 0
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; CHECK: .LBB1_2:
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; CHECK: lfd
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; CHECK: lvx
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; CHECK: ld
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; CHECK: blr
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; CHECK-NOAV: @main
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; CHECK-NOAV-NOT: stvx
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; CHECK-NOAV: bcl
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; CHECK-NOAV: mflr
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; CHECK-NOAV: bl foo
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; CHECK-NOAV-NOT: lvx
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; CHECK-NOAV: blr
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}
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define signext i32 @main2() #0 {
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entry:
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%a = alloca i8, align 64
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call void @bar(i8* %a)
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = call i8* @llvm.frameaddress(i32 0)
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store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**)
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%1 = call i8* @llvm.stacksave()
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store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
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%2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
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%tobool = icmp ne i32 %2, 0
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br i1 %tobool, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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if.else: ; preds = %entry
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call void @foo()
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br label %if.end
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if.end: ; preds = %if.else
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store i32 0, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%3 = load i32* %retval
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ret i32 %3
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; CHECK: @main2
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; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
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; CHECK-DAG: std 31, env_sigill@toc@l([[REG]])
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; CHECK-DAG: addi [[REGB:[0-9]+]], [[REG]], env_sigill@toc@l
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; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
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; CHECK-DAG: std 1, 16([[REGB]])
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; CHECK-DAG: std 2, 24([[REGB]])
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; CHECK-DAG: std 30, 32([[REGB]])
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; CHECK: bcl 20, 31,
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; CHECK: blr
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}
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declare void @bar(i8*) #3
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declare i8* @llvm.frameaddress(i32) #2
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declare i8* @llvm.stacksave() #3
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declare i32 @llvm.eh.sjlj.setjmp(i8*) #3
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { noreturn nounwind }
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attributes #2 = { nounwind readnone }
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attributes #3 = { nounwind }
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