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fca7f5c585
The AAPCS states that values passed in registers must have a value as though they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is, loading scalars to vector registers and loading 1-element vectors is equivalent. The logic implemented here is to ensure that at all call boundaries and during formal argument lowering all vectors are treated as their bitwidth-based floating point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64, v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be generated during code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| Analysis | ||
| Assembler | ||
| Bindings | ||
| Bitcode | ||
| BugPoint | ||
| CodeGen | ||
| DebugInfo | ||
| ExecutionEngine | ||
| Feature | ||
| FileCheck | ||
| Instrumentation | ||
| Integer | ||
| JitListener | ||
| Linker | ||
| LTO | ||
| MC | ||
| Object | ||
| Other | ||
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| tools | ||
| Transforms | ||
| Unit | ||
| Verifier | ||
| YAMLParser | ||
| .clang-format | ||
| CMakeLists.txt | ||
| lit.cfg | ||
| lit.site.cfg.in | ||
| Makefile | ||
| Makefile.tests | ||
| TestRunner.sh | ||