mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
35ef913ec2
Add dag combiner code to recognize rotl, rotr Add ppc code to match rotl Targets should add rotl/rotr patterns if they have them git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
459 lines
19 KiB
TableGen
459 lines
19 KiB
TableGen
//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent interfaces used by SelectionDAG
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// instruction selection generators.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Selection DAG Type Constraint definitions.
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//
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// Note that the semantics of these constraints are hard coded into tblgen. To
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// modify or add constraints, you have to hack tblgen.
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//
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class SDTypeConstraint<int opnum> {
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int OperandNum = opnum;
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}
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// SDTCisVT - The specified operand has exactly this VT.
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class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
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ValueType VT = vt;
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}
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class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisInt - The specified operand is has integer type.
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class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisFP - The specified operand is has floating point type.
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class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
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// SDTCisSameAs - The two specified operands have identical types.
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class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
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int OtherOperandNum = OtherOp;
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}
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// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
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// smaller than the 'Other' operand.
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class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
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int OtherOperandNum = OtherOp;
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}
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class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
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int BigOperandNum = BigOp;
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}
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//===----------------------------------------------------------------------===//
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// Selection DAG Type Profile definitions.
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//
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// These use the constraints defined above to describe the type requirements of
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// the various nodes. These are not hard coded into tblgen, allowing targets to
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// add their own if needed.
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//
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// SDTypeProfile - This profile describes the type requirements of a Selection
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// DAG node.
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class SDTypeProfile<int numresults, int numoperands,
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list<SDTypeConstraint> constraints> {
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int NumResults = numresults;
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int NumOperands = numoperands;
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list<SDTypeConstraint> Constraints = constraints;
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}
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// Builtin profiles.
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def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
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def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
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def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
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def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
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def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
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def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
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]>;
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def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
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]>;
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def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
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]>;
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def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
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]>;
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def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
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SDTCisSameAs<0, 1>, SDTCisInt<0>
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]>;
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def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
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SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
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]>;
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def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
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SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
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]>;
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def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
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SDTCisSameAs<0, 1>, SDTCisFP<0>
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]>;
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def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
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SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
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]>;
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def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
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SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
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]>;
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def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
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SDTCisFP<0>, SDTCisInt<1>
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]>;
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def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
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SDTCisInt<0>, SDTCisFP<1>
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]>;
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def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
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SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
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SDTCisVTSmallerThanOp<2, 1>
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]>;
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def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
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SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
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]>;
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def SDTSelect : SDTypeProfile<1, 3, [ // select
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SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
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]>;
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def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
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SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
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SDTCisVT<5, OtherVT>
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]>;
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def SDTBr : SDTypeProfile<0, 1, [ // br
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SDTCisVT<0, OtherVT>
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]>;
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def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
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SDTCisInt<0>, SDTCisVT<1, OtherVT>
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]>;
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def SDTRet : SDTypeProfile<0, 0, []>; // ret
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def SDTReadPort : SDTypeProfile<1, 1, [ // readport
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SDTCisInt<0>, SDTCisInt<1>
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]>;
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def SDTWritePort : SDTypeProfile<0, 2, [ // writeport
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SDTCisInt<0>, SDTCisInt<1>
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]>;
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def SDTLoad : SDTypeProfile<1, 1, [ // load
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SDTCisPtrTy<1>
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]>;
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def SDTStore : SDTypeProfile<0, 2, [ // store
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SDTCisPtrTy<1>
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]>;
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def SDTExtLoad : SDTypeProfile<1, 3, [ // extload
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
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]>;
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def SDTIntExtLoad : SDTypeProfile<1, 3, [ // sextload, zextload
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SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
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]>;
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def SDTTruncStore : SDTypeProfile<0, 4, [ // truncstore
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SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
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]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Properties.
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//
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// Note: These are hard coded into tblgen.
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//
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class SDNodeProperty;
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def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
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def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
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def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
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def SDNPOutFlag : SDNodeProperty; // Write a flag result
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def SDNPInFlag : SDNodeProperty; // Read a flag operand
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def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
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//===----------------------------------------------------------------------===//
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// Selection DAG Node definitions.
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//
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class SDNode<string opcode, SDTypeProfile typeprof,
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list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
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string Opcode = opcode;
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string SDClass = sdclass;
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list<SDNodeProperty> Properties = props;
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SDTypeProfile TypeProfile = typeprof;
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}
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def set;
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def node;
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def srcvalue;
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def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
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def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
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def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
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def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
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def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
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def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
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def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
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"GlobalAddressSDNode">;
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def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
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"ConstantPoolSDNode">;
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def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
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"ConstantPoolSDNode">;
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def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
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"FrameIndexSDNode">;
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def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
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"FrameIndexSDNode">;
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def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
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"ExternalSymbolSDNode">;
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def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
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"ExternalSymbolSDNode">;
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def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
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[SDNPCommutative, SDNPAssociative]>;
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def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
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def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
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def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
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def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
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def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
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def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
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def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
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def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
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def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
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def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
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def and : SDNode<"ISD::AND" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def or : SDNode<"ISD::OR" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
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def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
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def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
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def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
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def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
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def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
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def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
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def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
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def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
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def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
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def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
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def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
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def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
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def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
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def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
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def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
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def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
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def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
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def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
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def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
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def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
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def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
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def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
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def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
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def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
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def select : SDNode<"ISD::SELECT" , SDTSelect>;
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def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
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def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
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def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
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def ret : SDNode<"ISD::RET" , SDTRet, [SDNPHasChain]>;
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def readport : SDNode<"ISD::READPORT" , SDTReadPort, [SDNPHasChain]>;
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def writeport : SDNode<"ISD::WRITEPORT" , SDTWritePort, [SDNPHasChain]>;
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def load : SDNode<"ISD::LOAD" , SDTLoad, [SDNPHasChain]>;
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def store : SDNode<"ISD::STORE" , SDTStore, [SDNPHasChain]>;
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// Do not use sextld and zextld directly. Use sextload and zextload (see
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// below) which pass in a dummy srcvalue node which tblgen will skip over.
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def sextld : SDNode<"ISD::SEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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def zextld : SDNode<"ISD::ZEXTLOAD" , SDTIntExtLoad, [SDNPHasChain]>;
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def extld : SDNode<"ISD::EXTLOAD" , SDTExtLoad, [SDNPHasChain]>;
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def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Condition Codes
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class CondCode; // ISD::CondCode enums
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def SETOEQ : CondCode; def SETOGT : CondCode;
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def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
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def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
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def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
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def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
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def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
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def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Transformation Functions.
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//
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// This mechanism allows targets to manipulate nodes in the output DAG once a
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// match has been formed. This is typically used to manipulate immediate
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// values.
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//
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class SDNodeXForm<SDNode opc, code xformFunction> {
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SDNode Opcode = opc;
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code XFormFunction = xformFunction;
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}
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def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Pattern Fragments.
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//
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// Pattern fragments are reusable chunks of dags that match specific things.
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// They can take arguments and have C++ predicates that control whether they
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// match. They are intended to make the patterns for common instructions more
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// compact and readable.
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//
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/// PatFrag - Represents a pattern fragment. This can match something on the
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/// DAG, frame a single node to multiply nested other fragments.
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///
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class PatFrag<dag ops, dag frag, code pred = [{}],
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SDNodeXForm xform = NOOP_SDNodeXForm> {
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dag Operands = ops;
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dag Fragment = frag;
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code Predicate = pred;
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SDNodeXForm OperandTransform = xform;
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}
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// PatLeaf's are pattern fragments that have no operands. This is just a helper
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// to define immediates and other common things concisely.
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class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
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: PatFrag<(ops), frag, pred, xform>;
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// Leaf fragments.
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def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
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def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
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def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
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// Other helper fragments.
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def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
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def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
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// extending load & truncstore fragments.
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def sextload : PatFrag<(ops node:$ptr, node:$vt),
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(sextld node:$ptr, srcvalue:$dummy, node:$vt)>;
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def zextload : PatFrag<(ops node:$ptr, node:$vt),
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(zextld node:$ptr, srcvalue:$dummy, node:$vt)>;
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def extload : PatFrag<(ops node:$ptr, node:$vt),
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(extld node:$ptr, srcvalue:$dummy, node:$vt)>;
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def truncstore : PatFrag<(ops node:$val, node:$ptr, node:$vt),
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(truncst node:$val, node:$ptr, srcvalue:$dummy,
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node:$vt)>;
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// setcc convenience fragments.
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def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETOEQ)>;
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def setogt : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETOGT)>;
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def setoge : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETOGE)>;
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def setolt : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETOLT)>;
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def setole : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETOLE)>;
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def setone : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETONE)>;
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def seto : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETO)>;
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def setuo : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETUO)>;
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def setueq : PatFrag<(ops node:$lhs, node:$rhs),
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(setcc node:$lhs, node:$rhs, SETUEQ)>;
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def setugt : PatFrag<(ops node:$lhs, node:$rhs),
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|
(setcc node:$lhs, node:$rhs, SETUGT)>;
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|
def setuge : PatFrag<(ops node:$lhs, node:$rhs),
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|
(setcc node:$lhs, node:$rhs, SETUGE)>;
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|
def setult : PatFrag<(ops node:$lhs, node:$rhs),
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|
(setcc node:$lhs, node:$rhs, SETULT)>;
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|
def setule : PatFrag<(ops node:$lhs, node:$rhs),
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|
(setcc node:$lhs, node:$rhs, SETULE)>;
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|
def setune : PatFrag<(ops node:$lhs, node:$rhs),
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|
(setcc node:$lhs, node:$rhs, SETUNE)>;
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|
def seteq : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETEQ)>;
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|
def setgt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETGT)>;
|
|
def setge : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETGE)>;
|
|
def setlt : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETLT)>;
|
|
def setle : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETLE)>;
|
|
def setne : PatFrag<(ops node:$lhs, node:$rhs),
|
|
(setcc node:$lhs, node:$rhs, SETNE)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Selection DAG Pattern Support.
|
|
//
|
|
// Patterns are what are actually matched against the target-flavored
|
|
// instruction selection DAG. Instructions defined by the target implicitly
|
|
// define patterns in most cases, but patterns can also be explicitly added when
|
|
// an operation is defined by a sequence of instructions (e.g. loading a large
|
|
// immediate value on RISC targets that do not support immediates as large as
|
|
// their GPRs).
|
|
//
|
|
|
|
class Pattern<dag patternToMatch, list<dag> resultInstrs> {
|
|
dag PatternToMatch = patternToMatch;
|
|
list<dag> ResultInstrs = resultInstrs;
|
|
list<Predicate> Predicates = []; // See class Instruction in Target.td.
|
|
}
|
|
|
|
// Pat - A simple (but common) form of a pattern, which produces a simple result
|
|
// not needing a full list.
|
|
class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Complex pattern definitions.
|
|
//
|
|
// Complex patterns, e.g. X86 addressing mode, requires pattern matching code
|
|
// in C++. NumOperands is the number of operands returned by the select function;
|
|
// SelectFunc is the name of the function used to pattern match the max. pattern;
|
|
// RootNodes are the list of possible root nodes of the sub-dags to match.
|
|
// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
|
|
//
|
|
class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = []> {
|
|
ValueType Ty = ty;
|
|
int NumOperands = numops;
|
|
string SelectFunc = fn;
|
|
list<SDNode> RootNodes = roots;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Dwarf support.
|
|
//
|
|
def SDT_dwarf_loc : SDTypeProfile<0, 3,
|
|
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
|
|
def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
|
|
|
|
def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
|
|
def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;
|
|
|
|
|
|
|