mirror of
https://github.com/c64scene-ar/llvm-6502.git
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facc9fb9ba
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5114 91177308-0d34-0410-b5e6-96231b3b80d8
287 lines
10 KiB
C++
287 lines
10 KiB
C++
//===-- X86/MachineCodeEmitter.cpp - Convert X86 code to machine code -----===//
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//
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// This file contains the pass that transforms the X86 machine instructions into
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// actual executable machine code.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Value.h"
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namespace {
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class Emitter : public FunctionPass {
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X86TargetMachine &TM;
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const X86InstrInfo ⅈ
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MachineCodeEmitter &MCE;
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public:
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Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
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: TM(tm), II(TM.getInstrInfo()), MCE(mce) {}
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bool runOnFunction(Function &F);
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virtual const char *getPassName() const {
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return "X86 Machine Code Emitter";
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}
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private:
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void emitBasicBlock(MachineBasicBlock &MBB);
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void emitInstruction(MachineInstr &MI);
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void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
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void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
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void emitConstant(unsigned Val, unsigned Size);
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void emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField);
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};
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
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/// machine code emitted. This uses a MAchineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool X86TargetMachine::addPassesToEmitMachineCode(PassManager &PM,
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MachineCodeEmitter &MCE) {
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PM.add(new Emitter(*this, MCE));
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return false;
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}
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bool Emitter::runOnFunction(Function &F) {
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MachineFunction &MF = MachineFunction::get(&F);
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MCE.startFunction(MF);
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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emitBasicBlock(*I);
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MCE.finishFunction(MF);
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return false;
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}
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void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
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MCE.startBasicBlock(MBB);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
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emitInstruction(**I);
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}
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namespace N86 { // Native X86 Register numbers...
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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static unsigned getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
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case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
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case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
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case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
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default:
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assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
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"Unknown physical register!");
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assert(0 && "Register allocator hasn't allocated reg correctly yet!");
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return 0;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
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}
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void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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MCE.emitByte(ModRMByte(SS, Index, Base));
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}
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void Emitter::emitConstant(unsigned Val, unsigned Size) {
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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MCE.emitByte(Val & 255);
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Val >>= 8;
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}
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}
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void Emitter::emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField) {
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const MachineOperand &BaseReg = MI.getOperand(Op);
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const MachineOperand &Scale = MI.getOperand(Op+1);
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const MachineOperand &IndexReg = MI.getOperand(Op+2);
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const MachineOperand &Disp = MI.getOperand(Op+3);
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
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if (BaseReg.getReg() == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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emitConstant(Disp.getImmedValue(), 4);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding... [REG+disp8]
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MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(Disp.getImmedValue(), 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
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emitConstant(Disp.getImmedValue(), 4);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg.getReg() == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (Disp.getImmedValue() == 0 && BaseReg.getReg() != X86::EBP) {
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// Emit no displacement ModR/M byte
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(Disp.getImmedValue())) {
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// Emit the disp8 encoding...
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MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImmedValue()];
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if (BaseReg.getReg() == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
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unsigned IndexRegNo = getX86RegNum(IndexReg.getReg());
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (Disp.getImmedValue() != 0 || ForceDisp32 || ForceDisp8) {
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if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
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emitConstant(Disp.getImmedValue(), 1);
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else
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emitConstant(Disp.getImmedValue(), 4);
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}
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}
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}
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unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ArgMask) {
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case X86II::Arg8: return 1;
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case X86II::Arg16: return 2;
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case X86II::Arg32: return 4;
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case X86II::Arg64: return 8;
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case X86II::Arg80: return 10;
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case X86II::Arg128: return 16;
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default: assert(0 && "Memory size not set!");
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return 0;
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}
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}
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void Emitter::emitInstruction(MachineInstr &MI) {
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unsigned Opcode = MI.getOpcode();
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const MachineInstrDescriptor &Desc = II.get(Opcode);
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// Emit instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
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if (Desc.TSFlags & X86II::TB) MCE.emitByte(0x0F);// Two-byte opcode prefix
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unsigned char BaseOpcode = II.getBaseOpcodeFor(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::RawFrm:
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MCE.emitByte(BaseOpcode);
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if (MI.getNumOperands() == 1) {
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assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
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MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
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}
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break;
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case X86II::AddRegFrm:
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MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
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if (MI.getNumOperands() == 2 && (MI.getOperand(1).isImmediate() ||
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MI.getOperand(1).getVRegValueOrNull())) {
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unsigned Size = sizeOfPtr(Desc);
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if (Value *V = MI.getOperand(1).getVRegValueOrNull()) {
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assert(Size == 4 && "Don't know how to emit non-pointer values!");
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MCE.emitGlobalAddress(cast<GlobalValue>(V));
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} else {
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emitConstant(MI.getOperand(1).getImmedValue(), Size);
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}
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}
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break;
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case X86II::MRMDestReg:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(0).getReg(),
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getX86RegNum(MI.getOperand(MI.getNumOperands()-1).getReg()));
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break;
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case X86II::MRMDestMem:
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
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break;
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case X86II::MRMSrcReg:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
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getX86RegNum(MI.getOperand(0).getReg()));
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break;
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case X86II::MRMSrcMem:
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, MI.getNumOperands()-4,
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getX86RegNum(MI.getOperand(0).getReg()));
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break;
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case X86II::MRMS0r: case X86II::MRMS1r:
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case X86II::MRMS2r: case X86II::MRMS3r:
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case X86II::MRMS4r: case X86II::MRMS5r:
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case X86II::MRMS6r: case X86II::MRMS7r:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(0).getReg(),
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(Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
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if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
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unsigned Size = sizeOfPtr(Desc);
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emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
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}
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break;
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}
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}
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