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5cfd4ddece
for a single "m" constraint; this is wrong because the opcode of a load or store would have to change in parallel. This patch makes it always compute addresses into a register, which is correct but not as efficient as possible. 7144566. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
994 B
LLVM
23 lines
994 B
LLVM
; RUN: llvm-as < %s | llc -march=ppc32 | grep add
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; ModuleID = '<stdin>'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
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target triple = "powerpc-apple-darwin10.0"
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; It is wrong on powerpc to substitute reg+reg for $0; the stw opcode
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; would have to change.
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@x = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
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define void @foo(i32 %y) nounwind ssp {
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entry:
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%y_addr = alloca i32 ; <i32*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i32 %y, i32* %y_addr
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%0 = load i32* %y_addr, align 4 ; <i32> [#uses=1]
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%1 = getelementptr inbounds [0 x i32]* @x, i32 0, i32 %0 ; <i32*> [#uses=1]
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call void asm sideeffect "isync\0A\09eieio\0A\09stw $1, $0", "=*o,r,~{memory}"(i32* %1, i32 0) nounwind
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br label %return
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return: ; preds = %entry
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ret void
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}
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