mirror of
https://github.com/c64scene-ar/llvm-6502.git
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75361b69f3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
273 lines
8.6 KiB
C++
273 lines
8.6 KiB
C++
//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmBackend.h"
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#include "X86.h"
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#include "X86FixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MachObjectWriter.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmBackend.h"
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using namespace llvm;
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namespace {
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static unsigned getFixupKindLog2Size(unsigned Kind) {
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switch (Kind) {
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default: assert(0 && "invalid fixup kind!");
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case X86::reloc_pcrel_1byte:
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case FK_Data_1: return 0;
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case FK_Data_2: return 1;
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case X86::reloc_pcrel_4byte:
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case X86::reloc_riprel_4byte:
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case X86::reloc_riprel_4byte_movq_load:
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case FK_Data_4: return 2;
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case FK_Data_8: return 3;
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}
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}
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class X86AsmBackend : public TargetAsmBackend {
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public:
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X86AsmBackend(const Target &T)
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: TargetAsmBackend(T) {}
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void ApplyFixup(const MCAsmFixup &Fixup, MCDataFragment &DF,
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uint64_t Value) const {
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unsigned Size = 1 << getFixupKindLog2Size(Fixup.Kind);
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assert(Fixup.Offset + Size <= DF.getContents().size() &&
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"Invalid fixup offset!");
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for (unsigned i = 0; i != Size; ++i)
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DF.getContents()[Fixup.Offset + i] = uint8_t(Value >> (i * 8));
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}
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bool MayNeedRelaxation(const MCInst &Inst,
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const SmallVectorImpl<MCAsmFixup> &Fixups) const;
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void RelaxInstruction(const MCInstFragment *IF, MCInst &Res) const;
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
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};
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static unsigned getRelaxedOpcode(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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case X86::JAE_1: return X86::JAE_4;
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case X86::JA_1: return X86::JA_4;
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case X86::JBE_1: return X86::JBE_4;
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case X86::JB_1: return X86::JB_4;
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case X86::JE_1: return X86::JE_4;
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case X86::JGE_1: return X86::JGE_4;
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case X86::JG_1: return X86::JG_4;
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case X86::JLE_1: return X86::JLE_4;
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case X86::JL_1: return X86::JL_4;
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case X86::JMP_1: return X86::JMP_4;
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case X86::JNE_1: return X86::JNE_4;
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case X86::JNO_1: return X86::JNO_4;
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case X86::JNP_1: return X86::JNP_4;
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case X86::JNS_1: return X86::JNS_4;
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case X86::JO_1: return X86::JO_4;
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case X86::JP_1: return X86::JP_4;
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case X86::JS_1: return X86::JS_4;
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}
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}
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bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst,
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const SmallVectorImpl<MCAsmFixup> &Fixups) const {
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// Check for a 1byte pcrel fixup, and enforce that we would know how to relax
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// this instruction.
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for (unsigned i = 0, e = Fixups.size(); i != e; ++i) {
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if (unsigned(Fixups[i].Kind) == X86::reloc_pcrel_1byte) {
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assert(getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode());
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return true;
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}
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}
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return false;
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}
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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// we can relax?
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void X86AsmBackend::RelaxInstruction(const MCInstFragment *IF,
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MCInst &Res) const {
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// The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
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unsigned RelaxedOp = getRelaxedOpcode(IF->getInst().getOpcode());
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if (RelaxedOp == IF->getInst().getOpcode()) {
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SmallString<256> Tmp;
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raw_svector_ostream OS(Tmp);
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IF->getInst().dump_pretty(OS);
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report_fatal_error("unexpected instruction to relax: " + OS.str());
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}
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Res = IF->getInst();
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Res.setOpcode(RelaxedOp);
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}
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/// WriteNopData - Write optimal nops to the output file for the \arg Count
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/// bytes. This returns the number of bytes written. It may return 0 if
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/// the \arg Count is more than the maximum optimal nops.
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///
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/// FIXME this is X86 32-bit specific and should move to a better place.
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bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
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static const uint8_t Nops[16][16] = {
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// nop
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{0x90},
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// xchg %ax,%ax
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{0x66, 0x90},
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// nopl (%[re]ax)
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{0x0f, 0x1f, 0x00},
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// nopl 0(%[re]ax)
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{0x0f, 0x1f, 0x40, 0x00},
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// nopl 0(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopw 0(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopl 0L(%[re]ax)
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{0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
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// nopl 0L(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopw 0L(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopw %cs:0L(%[re]ax,%[re]ax,1)
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{0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopl 0(%[re]ax,%[re]ax,1)
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// nopw 0(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x44, 0x00, 0x00,
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0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopw 0(%[re]ax,%[re]ax,1)
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// nopw 0(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
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0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopw 0(%[re]ax,%[re]ax,1)
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// nopl 0L(%[re]ax) */
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{0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
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0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
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// nopl 0L(%[re]ax)
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// nopl 0L(%[re]ax)
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{0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
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0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
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// nopl 0L(%[re]ax)
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// nopl 0L(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
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0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}
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};
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// Write an optimal sequence for the first 15 bytes.
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uint64_t OptimalCount = (Count < 16) ? Count : 15;
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for (uint64_t i = 0, e = OptimalCount; i != e; i++)
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OW->Write8(Nops[OptimalCount - 1][i]);
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// Finish with single byte nops.
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for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
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OW->Write8(0x90);
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return true;
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}
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/* *** */
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class ELFX86AsmBackend : public X86AsmBackend {
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public:
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ELFX86AsmBackend(const Target &T)
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: X86AsmBackend(T) {
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HasAbsolutizedSet = true;
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HasScatteredSymbols = true;
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}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return 0;
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}
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bool isVirtualSection(const MCSection &Section) const {
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const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
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return SE.getType() == MCSectionELF::SHT_NOBITS;;
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}
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};
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class DarwinX86AsmBackend : public X86AsmBackend {
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public:
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DarwinX86AsmBackend(const Target &T)
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: X86AsmBackend(T) {
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HasAbsolutizedSet = true;
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HasScatteredSymbols = true;
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}
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bool isVirtualSection(const MCSection &Section) const {
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const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
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return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
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SMO.getType() == MCSectionMachO::S_GB_ZEROFILL);
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}
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};
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class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
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public:
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DarwinX86_32AsmBackend(const Target &T)
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: DarwinX86AsmBackend(T) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return new MachObjectWriter(OS, /*Is64Bit=*/false);
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}
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};
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class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
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public:
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DarwinX86_64AsmBackend(const Target &T)
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: DarwinX86AsmBackend(T) {
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HasReliableSymbolDifference = true;
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}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return new MachObjectWriter(OS, /*Is64Bit=*/true);
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
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// Temporary labels in the string literals sections require symbols. The
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// issue is that the x86_64 relocation format does not allow symbol +
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// offset, and so the linker does not have enough information to resolve the
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// access to the appropriate atom unless an external relocation is used. For
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// non-cstring sections, we expect the compiler to use a non-temporary label
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// for anything that could have an addend pointing outside the symbol.
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//
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// See <rdar://problem/4765733>.
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const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
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return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
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}
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};
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}
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TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
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const std::string &TT) {
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switch (Triple(TT).getOS()) {
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case Triple::Darwin:
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return new DarwinX86_32AsmBackend(T);
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default:
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return new ELFX86AsmBackend(T);
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}
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}
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TargetAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
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const std::string &TT) {
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switch (Triple(TT).getOS()) {
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case Triple::Darwin:
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return new DarwinX86_64AsmBackend(T);
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default:
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return new ELFX86AsmBackend(T);
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}
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}
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