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fec1abaeab63bbb606fcfd80b4da7a1e19b0813a
llvm-6502/test/CodeGen
History
Robert Khasanov fec1abaeab [x86] Added _addcarry_ and _subborrow_ intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216164 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-21 09:43:43 +00:00
..
AArch64
Revert r216066, "Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type".
2014-08-21 01:59:30 +00:00
ARM
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
2014-08-21 00:19:16 +00:00
CPP
…
Generic
Use "weak alias" instead of "alias weak"
2014-07-30 22:51:54 +00:00
Hexagon
DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.
2014-08-06 00:21:25 +00:00
Inputs
…
Mips
Fix fmul combines with constant splat vectors
2014-08-16 10:14:19 +00:00
MSP430
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NVPTX
[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types
2014-07-23 20:23:49 +00:00
PowerPC
Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).
2014-08-19 19:05:24 +00:00
R600
R600/SI: Move all fabs / fneg handling to patterns
2014-08-15 18:42:22 +00:00
SPARC
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SystemZ
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Thumb
Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence
2014-08-20 23:38:50 +00:00
Thumb2
ARM: do not generate BLX instructions on Cortex-M CPUs.
2014-08-06 11:13:14 +00:00
X86
[x86] Added _addcarry_ and _subborrow_ intrinsics
2014-08-21 09:43:43 +00:00
XCore
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