mirror of
https://github.com/c64scene-ar/llvm-6502.git
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4633f1cde8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21424 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.2 KiB
C++
100 lines
3.2 KiB
C++
//===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaTargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Register the targets
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RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
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}
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namespace llvm {
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cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
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cl::desc("Enable LSR for Alpha (beta option!)"),
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cl::Hidden);
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}
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unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "alpha*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 5 && TT[0] == 'a' && TT[1] == 'l' && TT[2] == 'p' &&
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TT[3] == 'h' && TT[4] == 'a')
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return 20;
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if (M.getEndianness() == Module::LittleEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return 0;
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}
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AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL)
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: TargetMachine("alpha", IL, true),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) //TODO: check these
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{}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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if (EnableAlphaLSR) {
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PM.add(createLoopStrengthReducePass());
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PM.add(createCFGSimplificationPass());
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}
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// FIXME: Implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// FIXME: Implement the switch instruction in the instruction selector!
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PM.add(createLowerSwitchPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createAlphaPatternInstructionSelector(*this));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createPrologEpilogCodeInserter());
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// Must run branch selection immediately preceding the asm printer
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//PM.add(createAlphaBranchSelectionPass());
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PM.add(createAlphaCodePrinterPass(Out, *this));
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PM.add(createMachineCodeDeleter());
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return false;
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}
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