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529 lines
20 KiB
C++
529 lines
20 KiB
C++
//===-- X86PeepholeOpt.cpp - X86 Peephole Optimizer -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a peephole optimizer for the X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> NumPHOpts("x86-peephole",
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"Number of peephole optimization performed");
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Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded");
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struct PH : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
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};
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}
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FunctionPass *llvm::createX86PeepholeOptimizerPass() { return new PH(); }
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bool PH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I)) {
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Changed = true;
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++NumPHOpts;
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} else
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++I;
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return Changed;
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}
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bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I) {
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assert(I != MBB.end());
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MachineBasicBlock::iterator NextI = next(I);
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MachineInstr *MI = I;
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MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
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unsigned Size = 0;
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switch (MI->getOpcode()) {
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case X86::MOV8rr:
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case X86::MOV16rr:
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case X86::MOV32rr: // Destroy X = X copies...
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if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
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I = MBB.erase(I);
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return true;
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}
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return false;
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// A large number of X86 instructions have forms which take an 8-bit
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// immediate despite the fact that the operands are 16 or 32 bits. Because
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// this can save three bytes of code size (and icache space), we want to
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// shrink them if possible.
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case X86::IMUL16rri: case X86::IMUL32rri:
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assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
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if (MI->getOperand(2).isImmediate()) {
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int Val = MI->getOperand(2).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::IMUL16rri: Opcode = X86::IMUL16rri8; break;
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case X86::IMUL32rri: Opcode = X86::IMUL32rri8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned R1 = MI->getOperand(1).getReg();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
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return true;
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}
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}
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return false;
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#if 0
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case X86::IMUL16rmi: case X86::IMUL32rmi:
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assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
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if (MI->getOperand(5).isImmediate()) {
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int Val = MI->getOperand(5).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::IMUL16rmi: Opcode = X86::IMUL16rmi8; break;
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case X86::IMUL32rmi: Opcode = X86::IMUL32rmi8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned R1 = MI->getOperand(1).getReg();
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unsigned Scale = MI->getOperand(2).getImmedValue();
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unsigned R2 = MI->getOperand(3).getReg();
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unsigned Offset = MI->getOperand(4).getImmedValue();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
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addReg(R2).addSImm(Offset).addZImm((char)Val));
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return true;
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}
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}
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return false;
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#endif
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case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
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case X86::SUB16ri: case X86::SUB32ri:
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case X86::SBB16ri: case X86::SBB32ri:
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case X86::AND16ri: case X86::AND32ri:
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case X86::OR16ri: case X86::OR32ri:
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case X86::XOR16ri: case X86::XOR32ri:
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assert(MI->getNumOperands() == 2 && "These should all have 2 operands!");
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if (MI->getOperand(1).isImmediate()) {
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int Val = MI->getOperand(1).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::ADD16ri: Opcode = X86::ADD16ri8; break;
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case X86::ADD32ri: Opcode = X86::ADD32ri8; break;
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case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
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case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
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case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
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case X86::SBB16ri: Opcode = X86::SBB16ri8; break;
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case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
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case X86::AND16ri: Opcode = X86::AND16ri8; break;
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case X86::AND32ri: Opcode = X86::AND32ri8; break;
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case X86::OR16ri: Opcode = X86::OR16ri8; break;
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case X86::OR32ri: Opcode = X86::OR32ri8; break;
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case X86::XOR16ri: Opcode = X86::XOR16ri8; break;
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case X86::XOR32ri: Opcode = X86::XOR32ri8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 1, R0, MachineOperand::UseAndDef)
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.addZImm((char)Val));
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return true;
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}
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}
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return false;
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case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
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case X86::SUB16mi: case X86::SUB32mi:
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case X86::SBB16mi: case X86::SBB32mi:
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case X86::AND16mi: case X86::AND32mi:
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case X86::OR16mi: case X86::OR32mi:
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case X86::XOR16mi: case X86::XOR32mi:
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assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
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if (MI->getOperand(4).isImmediate()) {
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int Val = MI->getOperand(4).getImmedValue();
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// If the value is the same when signed extended from 8 bits...
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if (Val == (signed int)(signed char)Val) {
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unsigned Opcode;
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switch (MI->getOpcode()) {
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default: assert(0 && "Unknown opcode value!");
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case X86::ADD16mi: Opcode = X86::ADD16mi8; break;
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case X86::ADD32mi: Opcode = X86::ADD32mi8; break;
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case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
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case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
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case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
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case X86::SBB16mi: Opcode = X86::SBB16mi8; break;
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case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
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case X86::AND16mi: Opcode = X86::AND16mi8; break;
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case X86::AND32mi: Opcode = X86::AND32mi8; break;
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case X86::OR16mi: Opcode = X86::OR16mi8; break;
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case X86::OR32mi: Opcode = X86::OR32mi8; break;
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case X86::XOR16mi: Opcode = X86::XOR16mi8; break;
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case X86::XOR32mi: Opcode = X86::XOR32mi8; break;
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}
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unsigned R0 = MI->getOperand(0).getReg();
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unsigned Scale = MI->getOperand(1).getImmedValue();
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unsigned R1 = MI->getOperand(2).getReg();
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if (MI->getOperand(3).isImmediate()) {
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unsigned Offset = MI->getOperand(3).getImmedValue();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
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addReg(R1).addSImm(Offset).addZImm((char)Val));
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} else if (MI->getOperand(3).isGlobalAddress()) {
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GlobalValue *GA = MI->getOperand(3).getGlobal();
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int Offset = MI->getOperand(3).getOffset();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
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addReg(R1).addGlobalAddress(GA, false, Offset).
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addZImm((char)Val));
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}
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return true;
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}
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}
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return false;
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#if 0
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case X86::MOV32ri: Size++;
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case X86::MOV16ri: Size++;
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case X86::MOV8ri:
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// FIXME: We can only do this transformation if we know that flags are not
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// used here, because XOR clobbers the flags!
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if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
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int Val = MI->getOperand(1).getImmedValue();
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if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
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static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr};
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unsigned Reg = MI->getOperand(0).getReg();
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I = MBB.insert(MBB.erase(I),
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BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
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return true;
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} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
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// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
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}
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}
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return false;
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#endif
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case X86::BSWAP32r: // Change bswap EAX, bswap EAX into nothing
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if (Next->getOpcode() == X86::BSWAP32r &&
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MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
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I = MBB.erase(MBB.erase(I));
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return true;
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}
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return false;
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default:
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return false;
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}
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}
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namespace {
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class UseDefChains : public MachineFunctionPass {
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std::vector<MachineInstr*> DefiningInst;
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public:
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// getDefinition - Return the machine instruction that defines the specified
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// SSA virtual register.
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MachineInstr *getDefinition(unsigned Reg) {
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assert(MRegisterInfo::isVirtualRegister(Reg) &&
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"use-def chains only exist for SSA registers!");
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assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
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"Unknown register number!");
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assert(DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] &&
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"Unknown register number!");
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return DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister];
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}
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// setDefinition - Update the use-def chains to indicate that MI defines
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// register Reg.
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void setDefinition(unsigned Reg, MachineInstr *MI) {
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if (Reg-MRegisterInfo::FirstVirtualRegister >= DefiningInst.size())
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DefiningInst.resize(Reg-MRegisterInfo::FirstVirtualRegister+1);
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = MI;
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}
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// removeDefinition - Update the use-def chains to forget about Reg
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// entirely.
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void removeDefinition(unsigned Reg) {
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assert(getDefinition(Reg)); // Check validity
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DefiningInst[Reg-MRegisterInfo::FirstVirtualRegister] = 0;
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}
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = I->getOperand(i);
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if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
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MRegisterInfo::isVirtualRegister(MO.getReg()))
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setDefinition(MO.getReg(), I);
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}
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}
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return false;
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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std::vector<MachineInstr*>().swap(DefiningInst);
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}
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};
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RegisterAnalysis<UseDefChains> X("use-def-chains",
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"use-def chain construction for machine code");
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}
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namespace {
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Statistic<> NumSSAPHOpts("x86-ssa-peephole",
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"Number of SSA peephole optimization performed");
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/// SSAPH - This pass is an X86-specific, SSA-based, peephole optimizer. This
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/// pass is really a bad idea: a better instruction selector should completely
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/// supersume it. However, that will take some time to develop, and the
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/// simple things this can do are important now.
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class SSAPH : public MachineFunctionPass {
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UseDefChains *UDC;
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public:
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virtual bool runOnMachineFunction(MachineFunction &MF);
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bool PeepholeOptimize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &I);
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virtual const char *getPassName() const {
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return "X86 SSA-based Peephole Optimizer";
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}
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/// Propagate - Set MI[DestOpNo] = Src[SrcOpNo], optionally change the
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/// opcode of the instruction, then return true.
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bool Propagate(MachineInstr *MI, unsigned DestOpNo,
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MachineInstr *Src, unsigned SrcOpNo, unsigned NewOpcode = 0){
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MI->getOperand(DestOpNo) = Src->getOperand(SrcOpNo);
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if (NewOpcode) MI->setOpcode(NewOpcode);
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return true;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool OptimizeAddress(MachineInstr *MI, unsigned OpNo);
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/// getDefininingInst - If the specified operand is a read of an SSA
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/// register, return the machine instruction defining it, otherwise, return
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/// null.
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MachineInstr *getDefiningInst(MachineOperand &MO) {
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if (MO.isDef() || !MO.isRegister() ||
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!MRegisterInfo::isVirtualRegister(MO.getReg())) return 0;
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return UDC->getDefinition(MO.getReg());
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<UseDefChains>();
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AU.addPreserved<UseDefChains>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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FunctionPass *llvm::createX86SSAPeepholeOptimizerPass() { return new SSAPH(); }
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bool SSAPH::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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bool LocalChanged;
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UDC = &getAnalysis<UseDefChains>();
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do {
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LocalChanged = false;
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for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
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for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
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if (PeepholeOptimize(*BI, I)) {
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LocalChanged = true;
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++NumSSAPHOpts;
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} else
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++I;
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Changed |= LocalChanged;
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} while (LocalChanged);
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return Changed;
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}
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static bool isValidScaleAmount(unsigned Scale) {
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return Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8;
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}
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/// OptimizeAddress - If we can fold the addressing arithmetic for this
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/// memory instruction into the instruction itself, do so and return true.
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bool SSAPH::OptimizeAddress(MachineInstr *MI, unsigned OpNo) {
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MachineOperand &BaseRegOp = MI->getOperand(OpNo+0);
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MachineOperand &ScaleOp = MI->getOperand(OpNo+1);
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MachineOperand &IndexRegOp = MI->getOperand(OpNo+2);
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MachineOperand &DisplacementOp = MI->getOperand(OpNo+3);
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unsigned BaseReg = BaseRegOp.hasAllocatedReg() ? BaseRegOp.getReg() : 0;
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unsigned Scale = ScaleOp.getImmedValue();
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unsigned IndexReg = IndexRegOp.hasAllocatedReg() ? IndexRegOp.getReg() : 0;
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bool Changed = false;
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// If the base register is unset, and the index register is set with a scale
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// of 1, move it to be the base register.
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if (BaseRegOp.hasAllocatedReg() && BaseReg == 0 &&
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Scale == 1 && IndexReg != 0) {
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BaseRegOp.setReg(IndexReg);
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IndexRegOp.setReg(0);
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return true;
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}
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// Attempt to fold instructions used by the base register into the instruction
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if (MachineInstr *DefInst = getDefiningInst(BaseRegOp)) {
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switch (DefInst->getOpcode()) {
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case X86::MOV32ri:
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// If there is no displacement set for this instruction set one now.
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// FIXME: If we can fold two immediates together, we should do so!
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if (DisplacementOp.isImmediate() && !DisplacementOp.getImmedValue()) {
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if (DefInst->getOperand(1).isImmediate()) {
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BaseRegOp.setReg(0);
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return Propagate(MI, OpNo+3, DefInst, 1);
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}
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}
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break;
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case X86::ADD32rr:
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// If the source is a register-register add, and we do not yet have an
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// index register, fold the add into the memory address.
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if (IndexReg == 0) {
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BaseRegOp = DefInst->getOperand(1);
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IndexRegOp = DefInst->getOperand(2);
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ScaleOp.setImmedValue(1);
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return true;
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}
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break;
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case X86::SHL32ri:
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// If this shift could be folded into the index portion of the address if
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// it were the index register, move it to the index register operand now,
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// so it will be folded in below.
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if ((Scale == 1 || (IndexReg == 0 && IndexRegOp.hasAllocatedReg())) &&
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DefInst->getOperand(2).getImmedValue() < 4) {
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std::swap(BaseRegOp, IndexRegOp);
|
|
ScaleOp.setImmedValue(1); Scale = 1;
|
|
std::swap(IndexReg, BaseReg);
|
|
Changed = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Attempt to fold instructions used by the index into the instruction
|
|
if (MachineInstr *DefInst = getDefiningInst(IndexRegOp)) {
|
|
switch (DefInst->getOpcode()) {
|
|
case X86::SHL32ri: {
|
|
// Figure out what the resulting scale would be if we folded this shift.
|
|
unsigned ResScale = Scale * (1 << DefInst->getOperand(2).getImmedValue());
|
|
if (isValidScaleAmount(ResScale)) {
|
|
IndexRegOp = DefInst->getOperand(1);
|
|
ScaleOp.setImmedValue(ResScale);
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &I) {
|
|
MachineBasicBlock::iterator NextI = next(I);
|
|
|
|
MachineInstr *MI = I;
|
|
MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
|
|
|
|
bool Changed = false;
|
|
|
|
const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo();
|
|
|
|
// Scan the operands of this instruction. If any operands are
|
|
// register-register copies, replace the operand with the source.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
|
|
// Is this an SSA register use?
|
|
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) {
|
|
// If the operand is a vreg-vreg copy, it is always safe to replace the
|
|
// source value with the input operand.
|
|
unsigned Source, Dest;
|
|
if (TII.isMoveInstr(*DefInst, Source, Dest)) {
|
|
// Don't propagate physical registers into any instructions.
|
|
if (DefInst->getOperand(1).isRegister() &&
|
|
MRegisterInfo::isVirtualRegister(Source)) {
|
|
MI->getOperand(i).setReg(Source);
|
|
Changed = true;
|
|
++NumPHMoves;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// Perform instruction specific optimizations.
|
|
switch (MI->getOpcode()) {
|
|
|
|
// Register to memory stores. Format: <base,scale,indexreg,immdisp>, srcreg
|
|
case X86::MOV32mr: case X86::MOV16mr: case X86::MOV8mr:
|
|
case X86::MOV32mi: case X86::MOV16mi: case X86::MOV8mi:
|
|
// Check to see if we can fold the source instruction into this one...
|
|
if (MachineInstr *SrcInst = getDefiningInst(MI->getOperand(4))) {
|
|
switch (SrcInst->getOpcode()) {
|
|
// Fold the immediate value into the store, if possible.
|
|
case X86::MOV8ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV8mi);
|
|
case X86::MOV16ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV16mi);
|
|
case X86::MOV32ri: return Propagate(MI, 4, SrcInst, 1, X86::MOV32mi);
|
|
default: break;
|
|
}
|
|
}
|
|
|
|
// If we can optimize the addressing expression, do so now.
|
|
if (OptimizeAddress(MI, 0))
|
|
return true;
|
|
break;
|
|
|
|
case X86::MOV32rm:
|
|
case X86::MOV16rm:
|
|
case X86::MOV8rm:
|
|
// If we can optimize the addressing expression, do so now.
|
|
if (OptimizeAddress(MI, 1))
|
|
return true;
|
|
break;
|
|
|
|
default: break;
|
|
}
|
|
|
|
return Changed;
|
|
}
|