llvm-6502/test/CodeGen
Michael Liao 9d293f1f68 Fix PR17764
- When selecting BLEND from vselect, the operands need swapping as due to the
  difference between vselect and SSE/AVX's BLEND insn



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193900 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-02 00:10:02 +00:00
..
AArch64 [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 2013-10-31 22:36:59 +00:00
ARM [ARM] Add Virtualization subtarget feature and more build attributes in this area 2013-11-01 13:27:35 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests 2013-10-30 15:45:42 +00:00
MSP430
NVPTX
PowerPC
R600 Fix CodeGen for unaligned loads with address spaces 2013-10-30 23:30:05 +00:00
SPARC SparcV9 doesnt have rem instruction either. 2013-10-31 19:22:33 +00:00
SystemZ [SystemZ] Automatically detect zEC12 and z196 hosts 2013-10-31 12:14:17 +00:00
Thumb
Thumb2
X86 Fix PR17764 2013-11-02 00:10:02 +00:00
XCore