mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e1820a6a4e
Summary: This is a white lie to workaround a widespread bug in the -mfp64 implementation. The problem is that none of the 32-bit fpu ops mention the fact that they clobber the upper 32-bits of the 64-bit FPR. This allows MFHC1 to be scheduled on the wrong side of most 32-bit FPU ops. Fixing that requires a major overhaul of the FPU implementation which can't be done right now due to time constraints. MFHC1 is one of two affected instructions. These instructions are the only FPU instructions that don't read or write the lower 32-bits. We therefore pretend that it reads the bottom 32-bits to artificially create a dependency and prevent the scheduler changing the behaviour of the code. The other instruction is MTHC1 which will be fixed once I've have found a failing test case for it. The testcase is test-suite/SingleSource/UnitTests/Vector/simple.c when given TARGET_CFLAGS="-mips32r2 -mfp64 -mmsa". Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2966 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203464 91177308-0d34-0410-b5e6-96231b3b80d8
585 lines
22 KiB
C++
585 lines
22 KiB
C++
//===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSEInstrInfo.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm,
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tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
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RI(*tm.getSubtargetImpl()),
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IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
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const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
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return RI;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsSEInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
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(Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsSEInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
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(Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0, ZeroReg = 0;
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if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::GPR32RegClass.contains(SrcReg))
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Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
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else if (Mips::CCRRegClass.contains(SrcReg))
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Opc = Mips::CFC1;
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else if (Mips::FGR32RegClass.contains(SrcReg))
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Opc = Mips::MFC1;
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else if (Mips::HI32RegClass.contains(SrcReg))
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Opc = Mips::MFHI, SrcReg = 0;
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else if (Mips::LO32RegClass.contains(SrcReg))
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Opc = Mips::MFLO, SrcReg = 0;
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else if (Mips::HI32DSPRegClass.contains(SrcReg))
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Opc = Mips::MFHI_DSP;
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else if (Mips::LO32DSPRegClass.contains(SrcReg))
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Opc = Mips::MFLO_DSP;
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else if (Mips::DSPCCRegClass.contains(SrcReg)) {
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BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
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.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
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return;
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}
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else if (Mips::MSACtrlRegClass.contains(SrcReg))
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Opc = Mips::CFCMSA;
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}
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else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
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if (Mips::CCRRegClass.contains(DestReg))
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Opc = Mips::CTC1;
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else if (Mips::FGR32RegClass.contains(DestReg))
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Opc = Mips::MTC1;
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else if (Mips::HI32RegClass.contains(DestReg))
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Opc = Mips::MTHI, DestReg = 0;
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else if (Mips::LO32RegClass.contains(DestReg))
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Opc = Mips::MTLO, DestReg = 0;
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else if (Mips::HI32DSPRegClass.contains(DestReg))
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Opc = Mips::MTHI_DSP;
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else if (Mips::LO32DSPRegClass.contains(DestReg))
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Opc = Mips::MTLO_DSP;
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else if (Mips::DSPCCRegClass.contains(DestReg)) {
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BuildMI(MBB, I, DL, get(Mips::WRDSP))
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.addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
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.addReg(DestReg, RegState::ImplicitDefine);
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return;
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}
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else if (Mips::MSACtrlRegClass.contains(DestReg))
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Opc = Mips::CTCMSA;
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}
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else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_S;
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else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D32;
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else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D64;
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else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::GPR64RegClass.contains(SrcReg))
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Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
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else if (Mips::HI64RegClass.contains(SrcReg))
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Opc = Mips::MFHI64, SrcReg = 0;
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else if (Mips::LO64RegClass.contains(SrcReg))
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Opc = Mips::MFLO64, SrcReg = 0;
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else if (Mips::FGR64RegClass.contains(SrcReg))
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Opc = Mips::DMFC1;
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}
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else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
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if (Mips::HI64RegClass.contains(DestReg))
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Opc = Mips::MTHI64, DestReg = 0;
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else if (Mips::LO64RegClass.contains(DestReg))
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Opc = Mips::MTLO64, DestReg = 0;
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else if (Mips::FGR64RegClass.contains(DestReg))
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Opc = Mips::DMTC1;
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}
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else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
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if (Mips::MSA128BRegClass.contains(SrcReg))
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Opc = Mips::MOVE_V;
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}
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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if (ZeroReg)
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MIB.addReg(ZeroReg);
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}
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void MipsSEInstrInfo::
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storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
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int64_t Offset) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (Mips::GPR32RegClass.hasSubClassEq(RC))
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Opc = Mips::SW;
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else if (Mips::GPR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SD;
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else if (Mips::ACC64RegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_ACC64;
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else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_ACC64DSP;
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else if (Mips::ACC128RegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_ACC128;
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else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
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Opc = Mips::STORE_CCOND_DSP;
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else if (Mips::FGR32RegClass.hasSubClassEq(RC))
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Opc = Mips::SWC1;
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else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SDC1;
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else if (Mips::FGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::SDC164;
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else if (RC->hasType(MVT::v16i8))
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Opc = Mips::ST_B;
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else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
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Opc = Mips::ST_H;
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else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
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Opc = Mips::ST_W;
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else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
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Opc = Mips::ST_D;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
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}
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void MipsSEInstrInfo::
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loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, int64_t Offset) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (Mips::GPR32RegClass.hasSubClassEq(RC))
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Opc = Mips::LW;
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else if (Mips::GPR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LD;
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else if (Mips::ACC64RegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_ACC64;
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else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_ACC64DSP;
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else if (Mips::ACC128RegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_ACC128;
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else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
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Opc = Mips::LOAD_CCOND_DSP;
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else if (Mips::FGR32RegClass.hasSubClassEq(RC))
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Opc = Mips::LWC1;
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else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LDC1;
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else if (Mips::FGR64RegClass.hasSubClassEq(RC))
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Opc = Mips::LDC164;
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else if (RC->hasType(MVT::v16i8))
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Opc = Mips::LD_B;
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else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
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Opc = Mips::LD_H;
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else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
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Opc = Mips::LD_W;
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else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
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Opc = Mips::LD_D;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
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.addMemOperand(MMO);
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}
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bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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MachineBasicBlock &MBB = *MI->getParent();
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switch(MI->getDesc().getOpcode()) {
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default:
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return false;
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case Mips::RetRA:
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expandRetRA(MBB, MI, Mips::RET);
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break;
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case Mips::PseudoMFHI:
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expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
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break;
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case Mips::PseudoMFLO:
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expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
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break;
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case Mips::PseudoMFHI64:
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expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
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break;
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case Mips::PseudoMFLO64:
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expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
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break;
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case Mips::PseudoMTLOHI:
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expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
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break;
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case Mips::PseudoMTLOHI64:
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expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
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break;
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case Mips::PseudoMTLOHI_DSP:
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expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
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break;
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case Mips::PseudoCVT_S_W:
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expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
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break;
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case Mips::PseudoCVT_D32_W:
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expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
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break;
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case Mips::PseudoCVT_S_L:
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expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
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break;
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case Mips::PseudoCVT_D64_W:
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expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
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break;
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case Mips::PseudoCVT_D64_L:
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expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
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break;
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case Mips::BuildPairF64:
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expandBuildPairF64(MBB, MI, false);
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break;
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case Mips::BuildPairF64_64:
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expandBuildPairF64(MBB, MI, true);
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break;
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case Mips::ExtractElementF64:
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expandExtractElementF64(MBB, MI, false);
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break;
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case Mips::ExtractElementF64_64:
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expandExtractElementF64(MBB, MI, true);
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break;
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case Mips::MIPSeh_return32:
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case Mips::MIPSeh_return64:
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expandEhReturn(MBB, MI);
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break;
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}
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MBB.erase(MI);
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return true;
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}
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/// getOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BEQ: return Mips::BNE;
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case Mips::BNE: return Mips::BEQ;
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case Mips::BGTZ: return Mips::BLEZ;
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case Mips::BGEZ: return Mips::BLTZ;
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case Mips::BLTZ: return Mips::BGEZ;
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case Mips::BLEZ: return Mips::BGTZ;
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case Mips::BEQ64: return Mips::BNE64;
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case Mips::BNE64: return Mips::BEQ64;
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case Mips::BGTZ64: return Mips::BLEZ64;
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case Mips::BGEZ64: return Mips::BLTZ64;
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case Mips::BLTZ64: return Mips::BGEZ64;
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case Mips::BLEZ64: return Mips::BGTZ64;
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case Mips::BC1T: return Mips::BC1F;
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case Mips::BC1F: return Mips::BC1T;
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}
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}
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/// Adjust SP by Amount bytes.
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void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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if (isInt<16>(Amount))// addi sp, sp, amount
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BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
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else { // Expand immediate that doesn't fit in 16-bit.
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unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
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BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
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}
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}
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/// This function generates the sequence of instructions needed to get the
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/// result of adding register REG and immediate IMM.
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unsigned
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MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator II, DebugLoc DL,
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unsigned *NewImm) const {
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MipsAnalyzeImmediate AnalyzeImm;
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const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
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MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
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unsigned Size = STI.isABI_N64() ? 64 : 32;
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unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
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unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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const TargetRegisterClass *RC = STI.isABI_N64() ?
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&Mips::GPR64RegClass : &Mips::GPR32RegClass;
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bool LastInstrIsADDiu = NewImm;
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
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// The first instruction can be a LUi, which is different from other
|
|
// instructions (ADDiu, ORI and SLL) in that it does not have a register
|
|
// operand.
|
|
unsigned Reg = RegInfo.createVirtualRegister(RC);
|
|
|
|
if (Inst->Opc == LUi)
|
|
BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
|
|
else
|
|
BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
|
|
.addImm(SignExtend64<16>(Inst->ImmOpnd));
|
|
|
|
// Build the remaining instructions in Seq.
|
|
for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
|
|
BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
|
|
.addImm(SignExtend64<16>(Inst->ImmOpnd));
|
|
|
|
if (LastInstrIsADDiu)
|
|
*NewImm = Inst->ImmOpnd;
|
|
|
|
return Reg;
|
|
}
|
|
|
|
unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
|
|
return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
|
|
Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
|
|
Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
|
|
Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
|
|
Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
|
|
Opc == Mips::J) ?
|
|
Opc : 0;
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned Opc) const {
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
|
|
}
|
|
|
|
std::pair<bool, bool>
|
|
MipsSEInstrInfo::compareOpndSize(unsigned Opc,
|
|
const MachineFunction &MF) const {
|
|
const MCInstrDesc &Desc = get(Opc);
|
|
assert(Desc.NumOperands == 2 && "Unary instruction expected.");
|
|
const MipsRegisterInfo *RI = &getRegisterInfo();
|
|
unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
|
|
unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
|
|
|
|
return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned NewOpc) const {
|
|
BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned LoOpc,
|
|
unsigned HiOpc,
|
|
bool HasExplicitDef) const {
|
|
// Expand
|
|
// lo_hi pseudomtlohi $gpr0, $gpr1
|
|
// to these two instructions:
|
|
// mtlo $gpr0
|
|
// mthi $gpr1
|
|
|
|
DebugLoc DL = I->getDebugLoc();
|
|
const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
|
|
MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
|
|
MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
|
|
LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
|
|
HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
|
|
|
|
// Add lo/hi registers if the mtlo/hi instructions created have explicit
|
|
// def registers.
|
|
if (HasExplicitDef) {
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
|
|
unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
|
|
LoInst.addReg(DstLo, RegState::Define);
|
|
HiInst.addReg(DstHi, RegState::Define);
|
|
}
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
unsigned CvtOpc, unsigned MovOpc,
|
|
bool IsI64) const {
|
|
const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
|
|
const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
|
|
unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
|
|
unsigned KillSrc = getKillRegState(Src.isKill());
|
|
DebugLoc DL = I->getDebugLoc();
|
|
bool DstIsLarger, SrcIsLarger;
|
|
|
|
std::tie(DstIsLarger, SrcIsLarger) =
|
|
compareOpndSize(CvtOpc, *MBB.getParent());
|
|
|
|
if (DstIsLarger)
|
|
TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
|
|
|
|
if (SrcIsLarger)
|
|
DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
|
|
|
|
BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
|
|
BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
bool FP64) const {
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
unsigned SrcReg = I->getOperand(1).getReg();
|
|
unsigned N = I->getOperand(2).getImm();
|
|
DebugLoc dl = I->getDebugLoc();
|
|
|
|
assert(N < 2 && "Invalid immediate");
|
|
unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
|
|
unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
|
|
|
|
if (SubIdx == Mips::sub_hi && FP64) {
|
|
// FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to
|
|
// temporarily work around a widespread bug in the -mfp64 support.
|
|
// The problem is that none of the 32-bit fpu ops mention the fact
|
|
// that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
|
|
// requires a major overhaul of the FPU implementation which can't
|
|
// be done right now due to time constraints.
|
|
// MFHC1 is the only instruction that is affected since it is the
|
|
// only instruction that doesn't read the lower 32-bits. We therefore
|
|
// pretend that it reads the bottom 32-bits to artificially create a
|
|
// dependency and prevent the scheduler changing the behaviour of the
|
|
// code.
|
|
BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg(
|
|
SrcReg, RegState::Implicit);
|
|
} else
|
|
BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
bool FP64) const {
|
|
unsigned DstReg = I->getOperand(0).getReg();
|
|
unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
|
|
const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
|
|
DebugLoc dl = I->getDebugLoc();
|
|
const TargetRegisterInfo &TRI = getRegisterInfo();
|
|
|
|
// For FP32 mode:
|
|
// mtc1 Lo, $fp
|
|
// mtc1 Hi, $fp + 1
|
|
// For FP64 mode:
|
|
// mtc1 Lo, $fp
|
|
// mthc1 Hi, $fp
|
|
|
|
BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
|
|
.addReg(LoReg);
|
|
|
|
if (FP64)
|
|
BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
|
|
.addReg(HiReg);
|
|
else
|
|
BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
|
|
.addReg(HiReg);
|
|
}
|
|
|
|
void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
// This pseudo instruction is generated as part of the lowering of
|
|
// ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
|
|
// indirect jump to TargetReg
|
|
const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
|
|
unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
|
|
unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
|
|
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
|
|
unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
|
|
unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
|
|
unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
|
|
unsigned OffsetReg = I->getOperand(0).getReg();
|
|
unsigned TargetReg = I->getOperand(1).getReg();
|
|
|
|
// addu $ra, $v0, $zero
|
|
// addu $sp, $sp, $v1
|
|
// jr $ra
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
|
|
.addReg(TargetReg).addReg(ZERO);
|
|
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
|
|
.addReg(TargetReg).addReg(ZERO);
|
|
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
|
|
.addReg(SP).addReg(OffsetReg);
|
|
BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
|
|
}
|
|
|
|
const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
|
|
return new MipsSEInstrInfo(TM);
|
|
}
|