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https://github.com/jeremysrand/llvm-65816.git
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83 lines
3.6 KiB
TableGen
83 lines
3.6 KiB
TableGen
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//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Intrinsic Definitions
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_tid : Intrinsic <[llvm_i32_ty], [], [IntrNoMem]>;
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def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
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// Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
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def int_SI_tbuffer_store : Intrinsic <
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[],
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
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llvm_i32_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // dfmt(imm)
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llvm_i32_ty, // nfmt(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[]>;
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// Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
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def int_SI_buffer_load_dword : Intrinsic <
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[llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[IntrReadArgMem]>;
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def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_sample : Sample;
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def int_SI_sampleb : Sample;
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def int_SI_sampled : Sample;
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def int_SI_samplel : Sample;
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def int_SI_imageload : Intrinsic <[llvm_v4i32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_resinfo : Intrinsic <[llvm_v4i32_ty], [llvm_i32_ty, llvm_v32i8_ty, llvm_i32_ty], [IntrNoMem]>;
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/* Interpolation Intrinsics */
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def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
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/* Control flow Intrinsics */
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def int_SI_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>;
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def int_SI_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_SI_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>;
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def int_SI_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>;
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def int_SI_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>;
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def int_SI_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>;
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def int_SI_end_cf : Intrinsic<[], [llvm_i64_ty], []>;
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}
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