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75 lines
3.4 KiB
TableGen
75 lines
3.4 KiB
TableGen
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//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
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// This file describes that machine information.
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//
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// |===========|==================================================|
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// | PIPELINE | Instruction Classes |
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// |===========|==================================================|
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// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
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// |-----------|--------------------------------------------------|
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// | SLOT1 | LD ST ALU32 |
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// |-----------|--------------------------------------------------|
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// | SLOT2 | XTYPE ALU32 J JR |
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// |-----------|--------------------------------------------------|
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// | SLOT3 | XTYPE ALU32 J CR |
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// |===========|==================================================|
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// Functional Units.
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def SLOT0 : FuncUnit;
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def SLOT1 : FuncUnit;
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def SLOT2 : FuncUnit;
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def SLOT3 : FuncUnit;
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// Endloop is a pseudo instruction that is encoded with 2 bits in a packet
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// rather than taking an execution slot. This special unit is needed
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// to schedule an ENDLOOP with 4 other instructions.
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def SLOT_ENDLOOP: FuncUnit;
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// Itinerary classes.
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def NV_V4 : InstrItinClass;
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def MEM_V4 : InstrItinClass;
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// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
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def PREFIX : InstrItinClass;
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def HexagonItinerariesV4 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
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InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,
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InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,
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InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<LD0 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,
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InstrItinData<ST0 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>,
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InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>,
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InstrItinData<ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>,
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InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>]>
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]>;
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def HexagonModelV4 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV4;
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let LoadLatency = 1;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V4 Resource Definitions -
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//===----------------------------------------------------------------------===//
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