More work to get a basic WDC65816 infrastructure in and compiling.

lib/Target/WDC65816/Makefile

@@ -12,7 +12,10 @@ LIBRARYNAME = LLVMWDC65816CodeGen
 TARGET = WDC65816
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES =
+BUILT_SOURCES = WDC65816GenRegisterInfo.inc WDC65816GenInstrInfo.inc \
+		WDC65816GenAsmWriter.inc WDC65816GenDAGISel.inc \
+		WDC65816GenSubtargetInfo.inc WDC65816GenCallingConv.inc \
+		WDC65816GenCodeEmitter.inc
 
 # DIRS = InstPrinter Disassembler AsmParser TargetInfo MCTargetDesc
 

lib/Target/WDC65816/WDC65816.h

@@ -24,7 +24,6 @@ namespace llvm {
     class formatted_raw_ostream;
     
     FunctionPass *createWDC65816ISelDag(WDC65816TargetMachine &TM);
-    FunctionPass *createWDC65816DelaySlotFillerPass(TargetMachine &TM);
     
 } // end namespace llvm;
 

lib/Target/WDC65816/WDC65816FrameLowering.cpp

@@ -0,0 +1,253 @@
+//===-- WDC65816FrameLowering.cpp - WDC65816 Frame Information ------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the WDC65816 implementation of TargetFrameLowering class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "WDC65816FrameLowering.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/Function.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#if 0 // JSR TODO - Do I need any of this?
+static cl::opt<bool>
+DisableLeafProc("disable-sparc-leaf-proc",
+                cl::init(false),
+                cl::desc("Disable Sparc leaf procedure optimization."),
+                cl::Hidden);
+
+
+void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
+                                          MachineBasicBlock &MBB,
+                                          MachineBasicBlock::iterator MBBI,
+                                          int NumBytes,
+                                          unsigned ADDrr,
+                                          unsigned ADDri) const {
+    
+    DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
+    const SparcInstrInfo &TII =
+    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+    
+    if (NumBytes >= -4096 && NumBytes < 4096) {
+        BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
+        .addReg(SP::O6).addImm(NumBytes);
+        return;
+    }
+    
+    // Emit this the hard way.  This clobbers G1 which we always know is
+    // available here.
+    if (NumBytes >= 0) {
+        // Emit nonnegative numbers with sethi + or.
+        // sethi %hi(NumBytes), %g1
+        // or %g1, %lo(NumBytes), %g1
+        // add %sp, %g1, %sp
+        BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
+        .addImm(HI22(NumBytes));
+        BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
+        .addReg(SP::G1).addImm(LO10(NumBytes));
+        BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
+        .addReg(SP::O6).addReg(SP::G1);
+        return ;
+    }
+    
+    // Emit negative numbers with sethi + xor.
+    // sethi %hix(NumBytes), %g1
+    // xor %g1, %lox(NumBytes), %g1
+    // add %sp, %g1, %sp
+    BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
+    .addImm(HIX22(NumBytes));
+    BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
+    .addReg(SP::G1).addImm(LOX10(NumBytes));
+    BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
+    .addReg(SP::O6).addReg(SP::G1);
+}
+
+void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
+    SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
+    
+    MachineBasicBlock &MBB = MF.front();
+    MachineFrameInfo *MFI = MF.getFrameInfo();
+    const SparcInstrInfo &TII =
+    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+    MachineBasicBlock::iterator MBBI = MBB.begin();
+    DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+    
+    // Get the number of bytes to allocate from the FrameInfo
+    int NumBytes = (int) MFI->getStackSize();
+    
+    unsigned SAVEri = SP::SAVEri;
+    unsigned SAVErr = SP::SAVErr;
+    if (FuncInfo->isLeafProc()) {
+        if (NumBytes == 0)
+            return;
+        SAVEri = SP::ADDri;
+        SAVErr = SP::ADDrr;
+    }
+    NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
+    emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
+    
+    MachineModuleInfo &MMI = MF.getMMI();
+    const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
+    MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
+    BuildMI(MBB, MBBI, dl, TII.get(SP::PROLOG_LABEL)).addSym(FrameLabel);
+    
+    unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
+    
+    // Emit ".cfi_def_cfa_register 30".
+    MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
+                                                            regFP));
+    // Emit ".cfi_window_save".
+    MMI.addFrameInst(MCCFIInstruction::createWindowSave(FrameLabel));
+    
+    unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
+    unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
+    // Emit ".cfi_register 15, 31".
+    MMI.addFrameInst(MCCFIInstruction::createRegister(FrameLabel,
+                                                      regOutRA,
+                                                      regInRA));
+}
+
+void SparcFrameLowering::
+eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator I) const {
+    if (!hasReservedCallFrame(MF)) {
+        MachineInstr &MI = *I;
+        int Size = MI.getOperand(0).getImm();
+        if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
+            Size = -Size;
+        
+        if (Size)
+            emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
+    }
+    MBB.erase(I);
+}
+
+
+void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
+                                      MachineBasicBlock &MBB) const {
+    SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
+    MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+    const SparcInstrInfo &TII =
+    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+    DebugLoc dl = MBBI->getDebugLoc();
+    assert(MBBI->getOpcode() == SP::RETL &&
+           "Can only put epilog before 'retl' instruction!");
+    if (!FuncInfo->isLeafProc()) {
+        BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
+        .addReg(SP::G0);
+        return;
+    }
+    MachineFrameInfo *MFI = MF.getFrameInfo();
+    
+    int NumBytes = (int) MFI->getStackSize();
+    if (NumBytes == 0)
+        return;
+    
+    NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
+    emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
+}
+
+bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
+    // Reserve call frame if there are no variable sized objects on the stack.
+    return !MF.getFrameInfo()->hasVarSizedObjects();
+}
+
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register.  This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
+    const MachineFrameInfo *MFI = MF.getFrameInfo();
+    return MF.getTarget().Options.DisableFramePointerElim(MF) ||
+    MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
+}
+
+
+static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
+{
+    
+    for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
+        if (MRI->isPhysRegUsed(reg))
+            return false;
+    
+    for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
+        if (MRI->isPhysRegUsed(reg))
+            return false;
+    
+    return true;
+}
+
+bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
+{
+    
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    MachineFrameInfo    *MFI = MF.getFrameInfo();
+    
+    return !(MFI->hasCalls()              // has calls
+             || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
+             || MRI.isPhysRegUsed(SP::O6) // %SP is used
+             || hasFP(MF));               // need %FP
+}
+
+void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
+    
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    
+    // Remap %i[0-7] to %o[0-7].
+    for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
+        if (!MRI.isPhysRegUsed(reg))
+            continue;
+        unsigned mapped_reg = (reg - SP::I0 + SP::O0);
+        assert(!MRI.isPhysRegUsed(mapped_reg));
+        
+        // Replace I register with O register.
+        MRI.replaceRegWith(reg, mapped_reg);
+        
+        // Mark the reg unused.
+        MRI.setPhysRegUnused(reg);
+    }
+    
+    // Rewrite MBB's Live-ins.
+    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
+         MBB != E; ++MBB) {
+        for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
+            if (!MBB->isLiveIn(reg))
+                continue;
+            MBB->removeLiveIn(reg);
+            MBB->addLiveIn(reg - SP::I0 + SP::O0);
+        }
+    }
+    
+    assert(verifyLeafProcRegUse(&MRI));
+#ifdef XDEBUG
+    MF.verify(0, "After LeafProc Remapping");
+#endif
+}
+
+void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
+(MachineFunction &MF, RegScavenger *RS) const {
+    
+    if (!DisableLeafProc && isLeafProc(MF)) {
+        SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
+        MFI->setLeafProc(true);
+        
+        remapRegsForLeafProc(MF);
+    }
+    
+}
+
+#endif

lib/Target/WDC65816/WDC65816FrameLowering.h

@@ -0,0 +1,59 @@
+//===-- WDC65816FrameLowering.h - Define frame lowering for Sparc --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef WDC65816_FRAMEINFO_H
+#define WDC65816_FRAMEINFO_H
+
+#include "WDC65816.h"
+#include "llvm/Target/TargetFrameLowering.h"
+
+namespace llvm {
+    
+    class WDC65816FrameLowering : public TargetFrameLowering {
+    public:
+        explicit WDC65816FrameLowering(void)
+        : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, 0) {}
+#if 0 // JSR TODO - do I need any of this?
+        /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
+        /// the function.
+        void emitPrologue(MachineFunction &MF) const;
+        void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+        
+        void eliminateCallFramePseudoInstr(MachineFunction &MF,
+                                           MachineBasicBlock &MBB,
+                                           MachineBasicBlock::iterator I) const;
+        
+        bool hasReservedCallFrame(const MachineFunction &MF) const;
+        bool hasFP(const MachineFunction &MF) const;
+        void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
+                                                  RegScavenger *RS = NULL) const;
+        
+    private:
+        // Remap input registers to output registers for leaf procedure.
+        void remapRegsForLeafProc(MachineFunction &MF) const;
+        
+        // Returns true if MF is a leaf procedure.
+        bool isLeafProc(MachineFunction &MF) const;
+        
+        
+        // Emits code for adjusting SP in function prologue/epilogue.
+        void emitSPAdjustment(MachineFunction &MF,
+                              MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI,
+                              int NumBytes, unsigned ADDrr, unsigned ADDri) const;
+#endif
+    };
+    
+} // End llvm namespace
+
+#endif

lib/Target/WDC65816/WDC65816InstrFormats.td

@@ -0,0 +1,232 @@
+//===- WDCInstrFormats.td - WDC 65816 Instruction Formats ----*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+
+class InstWDC<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
+  field bits<8> Inst;
+
+  let Namespace = "WDC";
+  
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+
+//===----------------------------------------------------------------------===//
+// Group #1 instructions in the WDC 65816
+//===----------------------------------------------------------------------===//
+
+class OpGrp1<bits<3> val> {
+  bits<3> Value = val;
+}
+
+def OpGrp1ADC     : OpGrp1<3>;
+def OpGrp1AND     : OpGrp1<1>;
+def OpGrp1CMP     : OpGrp1<6>;
+def OpGrp1EOR     : OpGrp1<2>;
+def OpGrp1LDA     : OpGrp1<5>;
+def OpGrp1ORA     : OpGrp1<0>;
+def OpGrp1SBC     : OpGrp1<7>;
+def OpGrp1STA     : OpGrp1<4>;
+
+
+class AddrModeGrp1<bits<5> val> {
+  bits<5> Value = val;
+}
+
+def AddrModeGrp1Imm               : AddrModeGrp1<9>;
+def AddrModeGrp1DP                : AddrModeGrp1<5>;
+def AddrModeGrp1Abs               : AddrModeGrp1<13>;
+def AddrModeGrp1DPIdxX            : AddrModeGrp1<21>;
+def AddrModeGrp1AbsIdxX           : AddrModeGrp1<29>;
+def AddrModeGrp1AbsIdxY           : AddrModeGrp1<25>;
+def AddrModeGrp1DPIdxIndirX       : AddrModeGrp1<1>;
+def AddrModeGrp1DPIndirIdxY       : AddrModeGrp1<17>;
+def AddrModeGrp1DPIndir           : AddrModeGrp1<18>;
+def AddrModeGrp1DPIndirLongIndY   : AddrModeGrp1<23>;
+def AddrModeGrp1DPIndirLong       : AddrModeGrp1<7>;
+def AddrModeGrp1AbsLong           : AddrModeGrp1<15>;
+def AddrModeGrp1AbsLongIdxX       : AddrModeGrp1<31>;
+def AddrModeGrp1StackRel          : AddrModeGrp1<3>;
+def AddrModeGrp1StackRelIndirIdxY : AddrModeGrp1<19>;
+
+
+// Group 1 instructions
+class Group1<OpGrp1 opVal, AddrModeGrp1 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstWDC<outs, ins, asmstr, pattern> {
+    OpGrp1 op = opVal;
+    AddrModeGrp1 addrMode = addrModeVal;
+   
+    let Inst{7-5} = op.Value;
+    let Inst{4-0}  = addrMode.Value;
+}
+
+//===----------------------------------------------------------------------===//
+// Group #2 instructions in the WDC 65816
+//===----------------------------------------------------------------------===//
+
+
+class OpGrp2<bits<3> val> {
+  bits<3> Value = val;
+}
+
+def OpGrp2ASL     : OpGrp2<0>;
+def OpGrp2DEC     : OpGrp2<6>;
+def OpGrp2INC     : OpGrp2<7>;
+def OpGrp2LSR     : OpGrp2<2>;
+def OpGrp2ROL     : OpGrp2<1>;
+def OpGrp2ROR     : OpGrp2<3>;
+def OpGrp2STXY    : OpGrp2<4>;
+def OpGrp2LDXY    : OpGrp2<5>;
+
+
+class AddrModeGrp2<bits<3> val> {
+  bits<3> Value = val;
+}
+
+def AddrModeGrp2Acc               : AddrModeGrp2<2>;
+def AddrModeGrp2DP                : AddrModeGrp2<1>;
+def AddrModeGrp2Abs               : AddrModeGrp2<3>;
+def AddrModeGrp2DPIdx             : AddrModeGrp2<5>;
+def AddrModeGrp2AbsIdx            : AddrModeGrp2<7>;
+def AddrModeGrp2Imm               : AddrModeGrp2<0>;
+
+// Group 2 instructions
+class Group2<OpGrp2 opVal, AddrModeGrp2 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstWDC<outs, ins, asmstr, pattern> {
+    OpGrp2 op = opVal;
+    AddrModeGrp2 addrMode = addrModeVal;
+   
+    let Inst{7-5} = op.Value;
+    let Inst{4-2} = addrMode.Value;
+    let Inst{1-0} = 2;
+}
+
+
+// Group 2 Y instructions
+class Group2_Y<OpGrp2 opVal, AddrModeGrp2 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : Group2<opVal, addrModeVal, outs, ins, asmstr, pattern> {
+    OpGrp2 op = opVal;
+    AddrModeGrp2 addrMode = addrModeVal;
+   
+    let Inst{7-5} = op.Value;
+    let Inst{4-2} = addrMode.Value;
+    let Inst{1-0} = 0;
+}
+
+
+
+//===----------------------------------------------------------------------===//
+// Group #3 instructions in the WDC 65816
+//===----------------------------------------------------------------------===//
+
+class OpGrp3<bits<8> val> {
+    bits<8> Value = val;
+}
+
+
+def OpGrp3BCC       : OpGrp3<0x90>;
+def OpGrp3BCS       : OpGrp3<0xB0>;
+def OpGrp3BEQ       : OpGrp3<0xF0>;
+def OpGrp3BITImm    : OpGrp3<0x89>;
+def OpGrp3BITAbs    : OpGrp3<0x2C>;
+def OpGrp3BITDp     : OpGrp3<0x24>;
+def OpGrp3BITAbsi   : OpGrp3<0x3C>;
+def OpGrp3BITDpi    : OpGrp3<0x34>;
+def OpGrp3BMI       : OpGrp3<0x30>;
+def OpGrp3BNE       : OpGrp3<0xD0>;
+def OpGrp3BPL       : OpGrp3<0x10>;
+def OpGrp3BRA       : OpGrp3<0x80>;
+def OpGrp3BRK       : OpGrp3<0x00>;
+def OpGrp3BRL       : OpGrp3<0x82>;
+def OpGrp3BVC       : OpGrp3<0x50>;
+def OpGrp3BVS       : OpGrp3<0x70>;
+def OpGrp3CLC       : OpGrp3<0x18>;
+def OpGrp3CLD       : OpGrp3<0xD8>;
+def OpGrp3CLI       : OpGrp3<0x58>;
+def OpGrp3CLV       : OpGrp3<0xB8>;
+def OpGrp3COP       : OpGrp3<0x02>;
+def OpGrp3CPXimm    : OpGrp3<0xE0>;
+def OpGrp3CPXabs    : OpGrp3<0xEC>;
+def OpGrp3CPXdp     : OpGrp3<0xE4>;
+def OpGrp3CPYimm    : OpGrp3<0xC0>;
+def OpGrp3CPYabs    : OpGrp3<0xCC>;
+def OpGrp3CPYdp     : OpGrp3<0xC4>;
+def OpGrp3DEX       : OpGrp3<0xCA>;
+def OpGrp3DEY       : OpGrp3<0x88>;
+def OpGrp3INX       : OpGrp3<0xE8>;
+def OpGrp3INY       : OpGrp3<0xC8>;
+def OpGrp3JMPabs    : OpGrp3<0x4C>;
+def OpGrp3JMPindir  : OpGrp3<0x6C>;
+def OpGrp3JMPindiri : OpGrp3<0x7C>;
+def OpGrp3JMLabs    : OpGrp3<0x5C>;
+def OpGrp3JMLindir  : OpGrp3<0xDC>;
+def OpGrp3JSL       : OpGrp3<0x22>;
+def OpGrp3JSRabs    : OpGrp3<0x20>;
+def OpGrp3JSRindiri : OpGrp3<0xFC>;
+def OpGrp3MVN       : OpGrp3<0x54>;
+def OpGrp3MVP       : OpGrp3<0x44>;
+def OpGrp3NOP       : OpGrp3<0xEA>;
+def OpGrp3PEA       : OpGrp3<0xF4>;
+def OpGrp3PEI       : OpGrp3<0xD4>;
+def OpGrp3PER       : OpGrp3<0x62>;
+def OpGrp3PHA       : OpGrp3<0x48>;
+def OpGrp3PHB       : OpGrp3<0x8B>;
+def OpGrp3PHD       : OpGrp3<0x0B>;
+def OpGrp3PHK       : OpGrp3<0x4B>;
+def OpGrp3PHP       : OpGrp3<0x08>;
+def OpGrp3PHX       : OpGrp3<0xDA>;
+def OpGrp3PHY       : OpGrp3<0x5A>;
+def OpGrp3PLA       : OpGrp3<0x68>;
+def OpGrp3PLB       : OpGrp3<0xAB>;
+def OpGrp3PLD       : OpGrp3<0x2B>;
+def OpGrp3PLP       : OpGrp3<0x28>;
+def OpGrp3PLX       : OpGrp3<0xFA>;
+def OpGrp3PLY       : OpGrp3<0x7A>;
+def OpGrp3REP       : OpGrp3<0xC2>;
+def OpGrp3RTI       : OpGrp3<0x40>;
+def OpGrp3RTL       : OpGrp3<0x6B>;
+def OpGrp3RTS       : OpGrp3<0x60>;
+def OpGrp3SEC       : OpGrp3<0x38>;
+def OpGrp3SED       : OpGrp3<0xF8>;
+def OpGrp3SEI       : OpGrp3<0x78>;
+def OpGrp3SEP       : OpGrp3<0xE2>;
+def OpGrp3STP       : OpGrp3<0xDB>;
+def OpGrp3STZabs    : OpGrp3<0x9C>;
+def OpGrp3STZdp     : OpGrp3<0x64>;
+def OpGrp3STZabsi   : OpGrp3<0x9E>;
+def OpGrp3STZdpi    : OpGrp3<0x74>;
+def OpGrp3TAX       : OpGrp3<0xAA>;
+def OpGrp3TAY       : OpGrp3<0xA8>;
+def OpGrp3TCD       : OpGrp3<0x5B>;
+def OpGrp3TCS       : OpGrp3<0x1B>;
+def OpGrp3TDC       : OpGrp3<0x7B>;
+def OpGrp3TRBabs    : OpGrp3<0x1C>;
+def OpGrp3TRBdp     : OpGrp3<0x14>;
+def OpGrp3TSBabs    : OpGrp3<0x0C>;
+def OpGrp3TSBdp     : OpGrp3<0x04>;
+def OpGrp3TSC       : OpGrp3<0x3B>;
+def OpGrp3TSX       : OpGrp3<0xBA>;
+def OpGrp3TXA       : OpGrp3<0x8A>;
+def OpGrp3TXS       : OpGrp3<0x9A>;
+def OpGrp3TXY       : OpGrp3<0x9B>;
+def OpGrp3TYA       : OpGrp3<0x98>;
+def OpGrp3TYX       : OpGrp3<0xB8>;
+def OpGrp3WAI       : OpGrp3<0xCB>;
+def OpGrp3WDM       : OpGrp3<0xCB>;
+def OpGrp3XBA       : OpGrp3<0xEB>;
+def OpGrp3XCE       : OpGrp3<0xFB>;
+
+
+class Group3<OpGrp3 opVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstWDC<outs, ins, asmstr, pattern> {
+    OpGrp3 op = opVal;
+   
+    let Inst = op.Value;
+}

lib/Target/WDC65816/WDC65816TargetMachine.cpp

@@ -31,10 +31,10 @@ WDC65816TargetMachine::WDC65816TargetMachine(const Target &T, StringRef TT,
                                        Reloc::Model RM, CodeModel::Model CM,
                                        CodeGenOpt::Level OL)
 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-DL(Subtarget.getDataLayout()),
-InstrInfo(Subtarget),
+DL("e-p:32:8:8-i16:8:8-f32:8:8-f68:8:8-n16"),
+InstrInfo(),
 TLInfo(*this), TSInfo(*this),
-FrameLowering(Subtarget) {
+FrameLowering() {
     initAsmInfo();
 }