From 91e7016b1f8c6ec874bb149618e9015ada6ebcd6 Mon Sep 17 00:00:00 2001
From: Jeremy Rand <jeremy@rand-family.com>
Date: Fri, 11 Jul 2014 23:47:17 -0400
Subject: [PATCH] More work to get a basic WDC65816 infrastructure in and
 compiling.

---
 lib/Target/WDC65816/Makefile                  |    5 +-
 lib/Target/WDC65816/WDC65816.h                |    1 -
 lib/Target/WDC65816/WDC65816FrameLowering.cpp |  253 +++
 lib/Target/WDC65816/WDC65816FrameLowering.h   |   59 +
 lib/Target/WDC65816/WDC65816ISelLowering.h    |    0
 lib/Target/WDC65816/WDC65816InstrFormats.td   |  232 +++
 lib/Target/WDC65816/WDC65816InstrInfo.td      | 1351 +++++++++++++++++
 lib/Target/WDC65816/WDC65816TargetMachine.cpp |    6 +-
 8 files changed, 1902 insertions(+), 5 deletions(-)
 create mode 100644 lib/Target/WDC65816/WDC65816FrameLowering.cpp
 create mode 100644 lib/Target/WDC65816/WDC65816FrameLowering.h
 create mode 100644 lib/Target/WDC65816/WDC65816ISelLowering.h
 create mode 100644 lib/Target/WDC65816/WDC65816InstrFormats.td
 create mode 100644 lib/Target/WDC65816/WDC65816InstrInfo.td

diff --git a/lib/Target/WDC65816/Makefile b/lib/Target/WDC65816/Makefile
index dd82f02a..378221f1 100644
--- a/lib/Target/WDC65816/Makefile
+++ b/lib/Target/WDC65816/Makefile
@@ -12,7 +12,10 @@ LIBRARYNAME = LLVMWDC65816CodeGen
 TARGET = WDC65816
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES =
+BUILT_SOURCES = WDC65816GenRegisterInfo.inc WDC65816GenInstrInfo.inc \
+		WDC65816GenAsmWriter.inc WDC65816GenDAGISel.inc \
+		WDC65816GenSubtargetInfo.inc WDC65816GenCallingConv.inc \
+		WDC65816GenCodeEmitter.inc
 
 # DIRS = InstPrinter Disassembler AsmParser TargetInfo MCTargetDesc
 
diff --git a/lib/Target/WDC65816/WDC65816.h b/lib/Target/WDC65816/WDC65816.h
index ae7852ad..2fbeff85 100644
--- a/lib/Target/WDC65816/WDC65816.h
+++ b/lib/Target/WDC65816/WDC65816.h
@@ -24,7 +24,6 @@ namespace llvm {
     class formatted_raw_ostream;
     
     FunctionPass *createWDC65816ISelDag(WDC65816TargetMachine &TM);
-    FunctionPass *createWDC65816DelaySlotFillerPass(TargetMachine &TM);
     
 } // end namespace llvm;
 
diff --git a/lib/Target/WDC65816/WDC65816FrameLowering.cpp b/lib/Target/WDC65816/WDC65816FrameLowering.cpp
new file mode 100644
index 00000000..1e9d9a08
--- /dev/null
+++ b/lib/Target/WDC65816/WDC65816FrameLowering.cpp
@@ -0,0 +1,253 @@
+//===-- WDC65816FrameLowering.cpp - WDC65816 Frame Information ------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the WDC65816 implementation of TargetFrameLowering class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "WDC65816FrameLowering.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/Function.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#if 0 // JSR TODO - Do I need any of this?
+static cl::opt<bool>
+DisableLeafProc("disable-sparc-leaf-proc",
+                cl::init(false),
+                cl::desc("Disable Sparc leaf procedure optimization."),
+                cl::Hidden);
+
+
+void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
+                                          MachineBasicBlock &MBB,
+                                          MachineBasicBlock::iterator MBBI,
+                                          int NumBytes,
+                                          unsigned ADDrr,
+                                          unsigned ADDri) const {
+    
+    DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
+    const SparcInstrInfo &TII =
+    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+    
+    if (NumBytes >= -4096 && NumBytes < 4096) {
+        BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
+        .addReg(SP::O6).addImm(NumBytes);
+        return;
+    }
+    
+    // Emit this the hard way.  This clobbers G1 which we always know is
+    // available here.
+    if (NumBytes >= 0) {
+        // Emit nonnegative numbers with sethi + or.
+        // sethi %hi(NumBytes), %g1
+        // or %g1, %lo(NumBytes), %g1
+        // add %sp, %g1, %sp
+        BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
+        .addImm(HI22(NumBytes));
+        BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
+        .addReg(SP::G1).addImm(LO10(NumBytes));
+        BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
+        .addReg(SP::O6).addReg(SP::G1);
+        return ;
+    }
+    
+    // Emit negative numbers with sethi + xor.
+    // sethi %hix(NumBytes), %g1
+    // xor %g1, %lox(NumBytes), %g1
+    // add %sp, %g1, %sp
+    BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
+    .addImm(HIX22(NumBytes));
+    BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
+    .addReg(SP::G1).addImm(LOX10(NumBytes));
+    BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
+    .addReg(SP::O6).addReg(SP::G1);
+}
+
+void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
+    SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
+    
+    MachineBasicBlock &MBB = MF.front();
+    MachineFrameInfo *MFI = MF.getFrameInfo();
+    const SparcInstrInfo &TII =
+    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+    MachineBasicBlock::iterator MBBI = MBB.begin();
+    DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+    
+    // Get the number of bytes to allocate from the FrameInfo
+    int NumBytes = (int) MFI->getStackSize();
+    
+    unsigned SAVEri = SP::SAVEri;
+    unsigned SAVErr = SP::SAVErr;
+    if (FuncInfo->isLeafProc()) {
+        if (NumBytes == 0)
+            return;
+        SAVEri = SP::ADDri;
+        SAVErr = SP::ADDrr;
+    }
+    NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
+    emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
+    
+    MachineModuleInfo &MMI = MF.getMMI();
+    const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
+    MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
+    BuildMI(MBB, MBBI, dl, TII.get(SP::PROLOG_LABEL)).addSym(FrameLabel);
+    
+    unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
+    
+    // Emit ".cfi_def_cfa_register 30".
+    MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
+                                                            regFP));
+    // Emit ".cfi_window_save".
+    MMI.addFrameInst(MCCFIInstruction::createWindowSave(FrameLabel));
+    
+    unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
+    unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
+    // Emit ".cfi_register 15, 31".
+    MMI.addFrameInst(MCCFIInstruction::createRegister(FrameLabel,
+                                                      regOutRA,
+                                                      regInRA));
+}
+
+void SparcFrameLowering::
+eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator I) const {
+    if (!hasReservedCallFrame(MF)) {
+        MachineInstr &MI = *I;
+        int Size = MI.getOperand(0).getImm();
+        if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
+            Size = -Size;
+        
+        if (Size)
+            emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
+    }
+    MBB.erase(I);
+}
+
+
+void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
+                                      MachineBasicBlock &MBB) const {
+    SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
+    MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+    const SparcInstrInfo &TII =
+    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
+    DebugLoc dl = MBBI->getDebugLoc();
+    assert(MBBI->getOpcode() == SP::RETL &&
+           "Can only put epilog before 'retl' instruction!");
+    if (!FuncInfo->isLeafProc()) {
+        BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
+        .addReg(SP::G0);
+        return;
+    }
+    MachineFrameInfo *MFI = MF.getFrameInfo();
+    
+    int NumBytes = (int) MFI->getStackSize();
+    if (NumBytes == 0)
+        return;
+    
+    NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
+    emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
+}
+
+bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
+    // Reserve call frame if there are no variable sized objects on the stack.
+    return !MF.getFrameInfo()->hasVarSizedObjects();
+}
+
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register.  This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
+    const MachineFrameInfo *MFI = MF.getFrameInfo();
+    return MF.getTarget().Options.DisableFramePointerElim(MF) ||
+    MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
+}
+
+
+static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
+{
+    
+    for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
+        if (MRI->isPhysRegUsed(reg))
+            return false;
+    
+    for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
+        if (MRI->isPhysRegUsed(reg))
+            return false;
+    
+    return true;
+}
+
+bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
+{
+    
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    MachineFrameInfo    *MFI = MF.getFrameInfo();
+    
+    return !(MFI->hasCalls()              // has calls
+             || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
+             || MRI.isPhysRegUsed(SP::O6) // %SP is used
+             || hasFP(MF));               // need %FP
+}
+
+void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
+    
+    MachineRegisterInfo &MRI = MF.getRegInfo();
+    
+    // Remap %i[0-7] to %o[0-7].
+    for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
+        if (!MRI.isPhysRegUsed(reg))
+            continue;
+        unsigned mapped_reg = (reg - SP::I0 + SP::O0);
+        assert(!MRI.isPhysRegUsed(mapped_reg));
+        
+        // Replace I register with O register.
+        MRI.replaceRegWith(reg, mapped_reg);
+        
+        // Mark the reg unused.
+        MRI.setPhysRegUnused(reg);
+    }
+    
+    // Rewrite MBB's Live-ins.
+    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
+         MBB != E; ++MBB) {
+        for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
+            if (!MBB->isLiveIn(reg))
+                continue;
+            MBB->removeLiveIn(reg);
+            MBB->addLiveIn(reg - SP::I0 + SP::O0);
+        }
+    }
+    
+    assert(verifyLeafProcRegUse(&MRI));
+#ifdef XDEBUG
+    MF.verify(0, "After LeafProc Remapping");
+#endif
+}
+
+void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
+(MachineFunction &MF, RegScavenger *RS) const {
+    
+    if (!DisableLeafProc && isLeafProc(MF)) {
+        SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
+        MFI->setLeafProc(true);
+        
+        remapRegsForLeafProc(MF);
+    }
+    
+}
+
+#endif
diff --git a/lib/Target/WDC65816/WDC65816FrameLowering.h b/lib/Target/WDC65816/WDC65816FrameLowering.h
new file mode 100644
index 00000000..dbf689d1
--- /dev/null
+++ b/lib/Target/WDC65816/WDC65816FrameLowering.h
@@ -0,0 +1,59 @@
+//===-- WDC65816FrameLowering.h - Define frame lowering for Sparc --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef WDC65816_FRAMEINFO_H
+#define WDC65816_FRAMEINFO_H
+
+#include "WDC65816.h"
+#include "llvm/Target/TargetFrameLowering.h"
+
+namespace llvm {
+    
+    class WDC65816FrameLowering : public TargetFrameLowering {
+    public:
+        explicit WDC65816FrameLowering(void)
+        : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, 0) {}
+#if 0 // JSR TODO - do I need any of this?
+        /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
+        /// the function.
+        void emitPrologue(MachineFunction &MF) const;
+        void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+        
+        void eliminateCallFramePseudoInstr(MachineFunction &MF,
+                                           MachineBasicBlock &MBB,
+                                           MachineBasicBlock::iterator I) const;
+        
+        bool hasReservedCallFrame(const MachineFunction &MF) const;
+        bool hasFP(const MachineFunction &MF) const;
+        void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
+                                                  RegScavenger *RS = NULL) const;
+        
+    private:
+        // Remap input registers to output registers for leaf procedure.
+        void remapRegsForLeafProc(MachineFunction &MF) const;
+        
+        // Returns true if MF is a leaf procedure.
+        bool isLeafProc(MachineFunction &MF) const;
+        
+        
+        // Emits code for adjusting SP in function prologue/epilogue.
+        void emitSPAdjustment(MachineFunction &MF,
+                              MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI,
+                              int NumBytes, unsigned ADDrr, unsigned ADDri) const;
+#endif
+    };
+    
+} // End llvm namespace
+
+#endif
diff --git a/lib/Target/WDC65816/WDC65816ISelLowering.h b/lib/Target/WDC65816/WDC65816ISelLowering.h
new file mode 100644
index 00000000..e69de29b
diff --git a/lib/Target/WDC65816/WDC65816InstrFormats.td b/lib/Target/WDC65816/WDC65816InstrFormats.td
new file mode 100644
index 00000000..3a7716f4
--- /dev/null
+++ b/lib/Target/WDC65816/WDC65816InstrFormats.td
@@ -0,0 +1,232 @@
+//===- WDCInstrFormats.td - WDC 65816 Instruction Formats ----*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+
+class InstWDC<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
+  field bits<8> Inst;
+
+  let Namespace = "WDC";
+  
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString   = asmstr;
+  let Pattern = pattern;
+}
+
+//===----------------------------------------------------------------------===//
+// Group #1 instructions in the WDC 65816
+//===----------------------------------------------------------------------===//
+
+class OpGrp1<bits<3> val> {
+  bits<3> Value = val;
+}
+
+def OpGrp1ADC     : OpGrp1<3>;
+def OpGrp1AND     : OpGrp1<1>;
+def OpGrp1CMP     : OpGrp1<6>;
+def OpGrp1EOR     : OpGrp1<2>;
+def OpGrp1LDA     : OpGrp1<5>;
+def OpGrp1ORA     : OpGrp1<0>;
+def OpGrp1SBC     : OpGrp1<7>;
+def OpGrp1STA     : OpGrp1<4>;
+
+
+class AddrModeGrp1<bits<5> val> {
+  bits<5> Value = val;
+}
+
+def AddrModeGrp1Imm               : AddrModeGrp1<9>;
+def AddrModeGrp1DP                : AddrModeGrp1<5>;
+def AddrModeGrp1Abs               : AddrModeGrp1<13>;
+def AddrModeGrp1DPIdxX            : AddrModeGrp1<21>;
+def AddrModeGrp1AbsIdxX           : AddrModeGrp1<29>;
+def AddrModeGrp1AbsIdxY           : AddrModeGrp1<25>;
+def AddrModeGrp1DPIdxIndirX       : AddrModeGrp1<1>;
+def AddrModeGrp1DPIndirIdxY       : AddrModeGrp1<17>;
+def AddrModeGrp1DPIndir           : AddrModeGrp1<18>;
+def AddrModeGrp1DPIndirLongIndY   : AddrModeGrp1<23>;
+def AddrModeGrp1DPIndirLong       : AddrModeGrp1<7>;
+def AddrModeGrp1AbsLong           : AddrModeGrp1<15>;
+def AddrModeGrp1AbsLongIdxX       : AddrModeGrp1<31>;
+def AddrModeGrp1StackRel          : AddrModeGrp1<3>;
+def AddrModeGrp1StackRelIndirIdxY : AddrModeGrp1<19>;
+
+
+// Group 1 instructions
+class Group1<OpGrp1 opVal, AddrModeGrp1 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstWDC<outs, ins, asmstr, pattern> {
+    OpGrp1 op = opVal;
+    AddrModeGrp1 addrMode = addrModeVal;
+   
+    let Inst{7-5} = op.Value;
+    let Inst{4-0}  = addrMode.Value;
+}
+
+//===----------------------------------------------------------------------===//
+// Group #2 instructions in the WDC 65816
+//===----------------------------------------------------------------------===//
+
+
+class OpGrp2<bits<3> val> {
+  bits<3> Value = val;
+}
+
+def OpGrp2ASL     : OpGrp2<0>;
+def OpGrp2DEC     : OpGrp2<6>;
+def OpGrp2INC     : OpGrp2<7>;
+def OpGrp2LSR     : OpGrp2<2>;
+def OpGrp2ROL     : OpGrp2<1>;
+def OpGrp2ROR     : OpGrp2<3>;
+def OpGrp2STXY    : OpGrp2<4>;
+def OpGrp2LDXY    : OpGrp2<5>;
+
+
+class AddrModeGrp2<bits<3> val> {
+  bits<3> Value = val;
+}
+
+def AddrModeGrp2Acc               : AddrModeGrp2<2>;
+def AddrModeGrp2DP                : AddrModeGrp2<1>;
+def AddrModeGrp2Abs               : AddrModeGrp2<3>;
+def AddrModeGrp2DPIdx             : AddrModeGrp2<5>;
+def AddrModeGrp2AbsIdx            : AddrModeGrp2<7>;
+def AddrModeGrp2Imm               : AddrModeGrp2<0>;
+
+// Group 2 instructions
+class Group2<OpGrp2 opVal, AddrModeGrp2 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstWDC<outs, ins, asmstr, pattern> {
+    OpGrp2 op = opVal;
+    AddrModeGrp2 addrMode = addrModeVal;
+   
+    let Inst{7-5} = op.Value;
+    let Inst{4-2} = addrMode.Value;
+    let Inst{1-0} = 2;
+}
+
+
+// Group 2 Y instructions
+class Group2_Y<OpGrp2 opVal, AddrModeGrp2 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : Group2<opVal, addrModeVal, outs, ins, asmstr, pattern> {
+    OpGrp2 op = opVal;
+    AddrModeGrp2 addrMode = addrModeVal;
+   
+    let Inst{7-5} = op.Value;
+    let Inst{4-2} = addrMode.Value;
+    let Inst{1-0} = 0;
+}
+
+
+
+//===----------------------------------------------------------------------===//
+// Group #3 instructions in the WDC 65816
+//===----------------------------------------------------------------------===//
+
+class OpGrp3<bits<8> val> {
+    bits<8> Value = val;
+}
+
+
+def OpGrp3BCC       : OpGrp3<0x90>;
+def OpGrp3BCS       : OpGrp3<0xB0>;
+def OpGrp3BEQ       : OpGrp3<0xF0>;
+def OpGrp3BITImm    : OpGrp3<0x89>;
+def OpGrp3BITAbs    : OpGrp3<0x2C>;
+def OpGrp3BITDp     : OpGrp3<0x24>;
+def OpGrp3BITAbsi   : OpGrp3<0x3C>;
+def OpGrp3BITDpi    : OpGrp3<0x34>;
+def OpGrp3BMI       : OpGrp3<0x30>;
+def OpGrp3BNE       : OpGrp3<0xD0>;
+def OpGrp3BPL       : OpGrp3<0x10>;
+def OpGrp3BRA       : OpGrp3<0x80>;
+def OpGrp3BRK       : OpGrp3<0x00>;
+def OpGrp3BRL       : OpGrp3<0x82>;
+def OpGrp3BVC       : OpGrp3<0x50>;
+def OpGrp3BVS       : OpGrp3<0x70>;
+def OpGrp3CLC       : OpGrp3<0x18>;
+def OpGrp3CLD       : OpGrp3<0xD8>;
+def OpGrp3CLI       : OpGrp3<0x58>;
+def OpGrp3CLV       : OpGrp3<0xB8>;
+def OpGrp3COP       : OpGrp3<0x02>;
+def OpGrp3CPXimm    : OpGrp3<0xE0>;
+def OpGrp3CPXabs    : OpGrp3<0xEC>;
+def OpGrp3CPXdp     : OpGrp3<0xE4>;
+def OpGrp3CPYimm    : OpGrp3<0xC0>;
+def OpGrp3CPYabs    : OpGrp3<0xCC>;
+def OpGrp3CPYdp     : OpGrp3<0xC4>;
+def OpGrp3DEX       : OpGrp3<0xCA>;
+def OpGrp3DEY       : OpGrp3<0x88>;
+def OpGrp3INX       : OpGrp3<0xE8>;
+def OpGrp3INY       : OpGrp3<0xC8>;
+def OpGrp3JMPabs    : OpGrp3<0x4C>;
+def OpGrp3JMPindir  : OpGrp3<0x6C>;
+def OpGrp3JMPindiri : OpGrp3<0x7C>;
+def OpGrp3JMLabs    : OpGrp3<0x5C>;
+def OpGrp3JMLindir  : OpGrp3<0xDC>;
+def OpGrp3JSL       : OpGrp3<0x22>;
+def OpGrp3JSRabs    : OpGrp3<0x20>;
+def OpGrp3JSRindiri : OpGrp3<0xFC>;
+def OpGrp3MVN       : OpGrp3<0x54>;
+def OpGrp3MVP       : OpGrp3<0x44>;
+def OpGrp3NOP       : OpGrp3<0xEA>;
+def OpGrp3PEA       : OpGrp3<0xF4>;
+def OpGrp3PEI       : OpGrp3<0xD4>;
+def OpGrp3PER       : OpGrp3<0x62>;
+def OpGrp3PHA       : OpGrp3<0x48>;
+def OpGrp3PHB       : OpGrp3<0x8B>;
+def OpGrp3PHD       : OpGrp3<0x0B>;
+def OpGrp3PHK       : OpGrp3<0x4B>;
+def OpGrp3PHP       : OpGrp3<0x08>;
+def OpGrp3PHX       : OpGrp3<0xDA>;
+def OpGrp3PHY       : OpGrp3<0x5A>;
+def OpGrp3PLA       : OpGrp3<0x68>;
+def OpGrp3PLB       : OpGrp3<0xAB>;
+def OpGrp3PLD       : OpGrp3<0x2B>;
+def OpGrp3PLP       : OpGrp3<0x28>;
+def OpGrp3PLX       : OpGrp3<0xFA>;
+def OpGrp3PLY       : OpGrp3<0x7A>;
+def OpGrp3REP       : OpGrp3<0xC2>;
+def OpGrp3RTI       : OpGrp3<0x40>;
+def OpGrp3RTL       : OpGrp3<0x6B>;
+def OpGrp3RTS       : OpGrp3<0x60>;
+def OpGrp3SEC       : OpGrp3<0x38>;
+def OpGrp3SED       : OpGrp3<0xF8>;
+def OpGrp3SEI       : OpGrp3<0x78>;
+def OpGrp3SEP       : OpGrp3<0xE2>;
+def OpGrp3STP       : OpGrp3<0xDB>;
+def OpGrp3STZabs    : OpGrp3<0x9C>;
+def OpGrp3STZdp     : OpGrp3<0x64>;
+def OpGrp3STZabsi   : OpGrp3<0x9E>;
+def OpGrp3STZdpi    : OpGrp3<0x74>;
+def OpGrp3TAX       : OpGrp3<0xAA>;
+def OpGrp3TAY       : OpGrp3<0xA8>;
+def OpGrp3TCD       : OpGrp3<0x5B>;
+def OpGrp3TCS       : OpGrp3<0x1B>;
+def OpGrp3TDC       : OpGrp3<0x7B>;
+def OpGrp3TRBabs    : OpGrp3<0x1C>;
+def OpGrp3TRBdp     : OpGrp3<0x14>;
+def OpGrp3TSBabs    : OpGrp3<0x0C>;
+def OpGrp3TSBdp     : OpGrp3<0x04>;
+def OpGrp3TSC       : OpGrp3<0x3B>;
+def OpGrp3TSX       : OpGrp3<0xBA>;
+def OpGrp3TXA       : OpGrp3<0x8A>;
+def OpGrp3TXS       : OpGrp3<0x9A>;
+def OpGrp3TXY       : OpGrp3<0x9B>;
+def OpGrp3TYA       : OpGrp3<0x98>;
+def OpGrp3TYX       : OpGrp3<0xB8>;
+def OpGrp3WAI       : OpGrp3<0xCB>;
+def OpGrp3WDM       : OpGrp3<0xCB>;
+def OpGrp3XBA       : OpGrp3<0xEB>;
+def OpGrp3XCE       : OpGrp3<0xFB>;
+
+
+class Group3<OpGrp3 opVal, dag outs, dag ins, string asmstr, list<dag> pattern>
+   : InstWDC<outs, ins, asmstr, pattern> {
+    OpGrp3 op = opVal;
+   
+    let Inst = op.Value;
+}
diff --git a/lib/Target/WDC65816/WDC65816InstrInfo.td b/lib/Target/WDC65816/WDC65816InstrInfo.td
new file mode 100644
index 00000000..e977b0e1
--- /dev/null
+++ b/lib/Target/WDC65816/WDC65816InstrInfo.td
@@ -0,0 +1,1351 @@
+//===- WDCInstrInfo.td - Target Description for WDC 65816 Target ------------===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file describes the WDC 65816 instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction format superclass
+//===----------------------------------------------------------------------===//
+
+include "WDC65816InstrFormats.td"
+
+//===----------------------------------------------------------------------===//
+// Feature predicates.
+//===----------------------------------------------------------------------===//
+
+
+
+//===----------------------------------------------------------------------===//
+// Instruction Pattern Stuff
+//===----------------------------------------------------------------------===//
+
+// Adressing modes.
+def ADDRabs : ComplexPattern<i16, 1, "SelectAbs", [], []>;
+def ADDRabsl : ComplexPattern<i32, 1, "SelectAbsLong", [], []>;
+def ADDRdp : ComplexPattern<i8, 1, "SelectDirectPage", [], []>;
+
+
+//===----------------------------------------------------------------------===//
+// WDC 65816 Flag Conditions
+//===----------------------------------------------------------------------===//
+
+// Note that these values must be kept in sync with the CCOp::CondCode enum
+// values.
+
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+
+// Group #1 Instructions
+
+// JSR TODO - Need to set all of the DAG patterns
+// JSR TODO - Addresses are 32-bit to llvm but can we toss the upper byte for long addressing modes which are 24-bit
+// JSR TODO - Need to specify flag behaviour, especially carry for ADC, SBC, CMP
+
+def ADCimm : Group1<OpGrp1ADC, AddrModeGrp1Imm,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16imm:$src2),
+                  "ADC #>$src2",
+                  [(set AccRegs:$dst, (add AccRegs:$src1, i16imm:$src2))]>;
+
+def ADCabs :  Group1<OpGrp1ADC, AddrModeGrp1Abs,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2),
+                  "ADC |$src2",
+                  [(set AccRegs:$dst, (add AccRegs:$src1, (load ADDRabs:$src2)))]>;   
+
+def ADCabsl :  Group1<OpGrp1ADC, AddrModeGrp1AbsLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2),
+                  "ADC >$src2",
+                  [(set AccRegs:$dst, (add AccRegs:$src1, (load ADDRabsl:$src2)))]>;  
+
+def ADCdp :  Group1<OpGrp1ADC, AddrModeGrp1DP,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ADC <$src2",
+                  [(set AccRegs:$dst, (add AccRegs:$src1, (load ADDRdp:$src2)))]>; 
+
+def ADCdpindir :  Group1<OpGrp1ADC, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ADC (<$src2)",
+                  []>;  
+
+def ADCdpindirl :  Group1<OpGrp1ADC, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ADC [<$src2]",
+                  []>;  
+
+def ADCabsix :  Group1<OpGrp1ADC, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "ADC |$src2,$src3",
+                  []>;   
+
+def ADCabsiy :  Group1<OpGrp1ADC, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "ADC |$src2,$src3",
+                  []>;  
+
+def ADCabsixl :  Group1<OpGrp1ADC, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "ADC >$src2,$src3",
+                  []>; 
+
+def ADCdpix :  Group1<OpGrp1ADC, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "ADC <$src2,$src3",
+                  []>;  
+
+def ADCdpiindirx :  Group1<OpGrp1ADC, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "ADC (<$src2,$src3)",
+                  []>; 
+
+def ADCdpindiriy :  Group1<OpGrp1ADC, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "ADC (<$src2),$src3",
+                  []>;
+
+def ADCdpindirliy :  Group1<OpGrp1ADC, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "ADC [<$src2],$src3",
+                  []>; 
+
+def ADCsr :  Group1<OpGrp1ADC, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ADC <$src2,S",
+                  []>;  
+
+def ADCsrindir :  Group1<OpGrp1ADC, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "ADC (<$src2,S),$src3",
+                  []>;                
+
+def ANDimm : Group1<OpGrp1AND, AddrModeGrp1Imm,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16imm:$src2),
+                  "AND #>$src2",
+                  [(set AccRegs:$dst, (and AccRegs:$src1, i16imm:$src2))]>;
+
+def ANDabs :  Group1<OpGrp1AND, AddrModeGrp1Abs,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2),
+                  "AND |$src2",
+                  [(set AccRegs:$dst, (and AccRegs:$src1, (load ADDRabs:$src2)))]>;   
+
+def ANDabsl :  Group1<OpGrp1AND, AddrModeGrp1AbsLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2),
+                  "AND >$src2",
+                  [(set AccRegs:$dst, (and AccRegs:$src1, (load ADDRabsl:$src2)))]>;  
+
+def ANDdp :  Group1<OpGrp1AND, AddrModeGrp1DP,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "AND <$src2",
+                  [(set AccRegs:$dst, (and AccRegs:$src1, (load ADDRdp:$src2)))]>; 
+
+def ANDdpindir :  Group1<OpGrp1AND, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "AND (<$src2)",
+                  []>;  
+
+def ANDdpindirl :  Group1<OpGrp1AND, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "AND [<$src2]",
+                  []>;  
+
+def ANDabsix :  Group1<OpGrp1AND, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "AND |$src2,$src3",
+                  []>;   
+
+def ANDabsiy :  Group1<OpGrp1AND, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "AND |$src2,$src3",
+                  []>;  
+
+def ANDabsixl :  Group1<OpGrp1AND, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "AND >$src2,$src3",
+                  []>; 
+
+def ANDdpix :  Group1<OpGrp1AND, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "AND <$src2,$src3",
+                  []>;  
+
+def ANDdpiindirx :  Group1<OpGrp1AND, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "AND (<$src2,$src3)",
+                  []>; 
+
+def ANDdpindiriy :  Group1<OpGrp1AND, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "AND (<$src2),$src3",
+                  []>;
+
+def ANDdpindirliy :  Group1<OpGrp1AND, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "AND [<$src2],$src2",
+                  []>; 
+
+def ANDsr :  Group1<OpGrp1AND, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "AND <$src2,S",
+                  []>;  
+
+def ANDsrindir :  Group1<OpGrp1AND, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "AND (<$src2,S),$src3",
+                  []>;  
+
+def CMPimm : Group1<OpGrp1CMP, AddrModeGrp1Imm,
+                  (outs ), (ins AccRegs:$src1, i16imm:$src2),
+                  "CMP #>$src2",
+                  []>;
+
+def CMPabs :  Group1<OpGrp1CMP, AddrModeGrp1Abs,
+                  (outs ), (ins AccRegs:$src1, i16mem:$src2),
+                  "CMP |$src2",
+                  []>;   
+
+def CMPabsl :  Group1<OpGrp1CMP, AddrModeGrp1AbsLong,
+                  (outs ), (ins AccRegs:$src1, i32mem:$src2),
+                  "CMP >$src2",
+                  []>;  
+
+def CMPdp :  Group1<OpGrp1CMP, AddrModeGrp1DP,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2),
+                  "CMP <$src2",
+                  []>; 
+
+def CMPdpindir :  Group1<OpGrp1CMP, AddrModeGrp1DPIndir,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2),
+                  "CMP (<$src2)",
+                  []>;  
+
+def CMPdpindirl :  Group1<OpGrp1CMP, AddrModeGrp1DPIndirLong,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2),
+                  "CMP [<$src2]",
+                  []>;  
+
+def CMPabsix :  Group1<OpGrp1CMP, AddrModeGrp1AbsIdxX,
+                  (outs ), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "CMP |$src2,$src3",
+                  []>;   
+
+def CMPabsiy :  Group1<OpGrp1CMP, AddrModeGrp1AbsIdxY,
+                  (outs ), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "CMP |$src2,$src3",
+                  []>;  
+
+def CMPabsixl :  Group1<OpGrp1CMP, AddrModeGrp1AbsLongIdxX,
+                  (outs ), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "CMP >$src2,$src3",
+                  []>; 
+
+def CMPdpix :  Group1<OpGrp1CMP, AddrModeGrp1DPIdxX,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "CMP <$src2,$src3",
+                  []>;  
+
+def CMPdpiindirx :  Group1<OpGrp1CMP, AddrModeGrp1DPIdxIndirX,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "CMP (<$src2,$src3)",
+                  []>; 
+
+def CMPdpindiriy :  Group1<OpGrp1CMP, AddrModeGrp1DPIndirIdxY,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "CMP (<$src2),$src3",
+                  []>;
+
+def CMPdpindirliy :  Group1<OpGrp1CMP, AddrModeGrp1DPIndirLongIdxY,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "CMP [<$src2],$src3",
+                  []>; 
+
+def CMPsr :  Group1<OpGrp1CMP, AddrModeGrp1StackRel,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2),
+                  "CMP <$src2,S",
+                  []>;  
+
+def CMPsrindir :  Group1<OpGrp1CMP, AddrModeGrp1StackRelIndirIdxY,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "CMP (<$src2,S),$src3",
+                  []>;                 
+
+def EORimm : Group1<OpGrp1EOR, AddrModeGrp1Imm,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16imm:$src2),
+                  "EOR #>$src2",
+                  [(set AccRegs:$dst, (xor AccRegs:$src1, i16imm:$src2))]>;
+
+def EORabs :  Group1<OpGrp1EOR, AddrModeGrp1Abs,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2),
+                  "EOR |$src2",
+                  [(set AccRegs:$dst, (xor AccRegs:$src1, (load ADDRabs:$src2)))]>;   
+
+def EORabsl :  Group1<OpGrp1EOR, AddrModeGrp1AbsLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2),
+                  "EOR >$src2",
+                  [(set AccRegs:$dst, (xor AccRegs:$src1, (load ADDRabsl:$src2)))]>;  
+
+def EORdp :  Group1<OpGrp1EOR, AddrModeGrp1DP,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "EOR <$src2",
+                  [(set AccRegs:$dst, (xor AccRegs:$src1, (load ADDRdp:$src2)))]>; 
+
+def EORdpindir :  Group1<OpGrp1EOR, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "EOR (<$src2)",
+                  []>;  
+
+def EORdpindirl :  Group1<OpGrp1EOR, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "EOR [<$src2]",
+                  []>;  
+
+def EORabsix :  Group1<OpGrp1EOR, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "EOR |$src2,$src3",
+                  []>;   
+
+def EORabsiy :  Group1<OpGrp1EOR, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "EOR |$src2,$src3",
+                  []>;  
+
+def EORabsixl :  Group1<OpGrp1EOR, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "EOR >$src2,$src3",
+                  []>; 
+
+def EORdpix :  Group1<OpGrp1EOR, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "EOR <$src2,$src3",
+                  []>;  
+
+def EORdpiindirx :  Group1<OpGrp1EOR, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "EOR (<$src2,$src3)",
+                  []>; 
+
+def EORdpindiriy :  Group1<OpGrp1EOR, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "EOR (<$src2),$src3",
+                  []>;
+
+def EORdpindirliy :  Group1<OpGrp1EOR, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "EOR [<$src2],$src2",
+                  []>; 
+
+def EORsr :  Group1<OpGrp1EOR, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "EOR <$src2,S",
+                  []>;  
+
+def EORsrindir :  Group1<OpGrp1EOR, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "EOR (<$src2,S),$src3",
+                  []>;                    
+
+def LDAimm : Group1<OpGrp1LDA, AddrModeGrp1Imm,
+                  (outs AccRegs:$dst), (ins i16imm:$src1),
+                  "LDA #>$src1",
+                  [(set AccRegs:$dst, i16imm:$src)]>;
+
+def LDAabs :  Group1<OpGrp1LDA, AddrModeGrp1Abs,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2),
+                  "LDA |$src2",
+                  [(set AccRegs:$dst, (load ADDRabs:$src2))]>;   
+
+def LDAabsl :  Group1<OpGrp1LDA, AddrModeGrp1AbsLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2),
+                  "LDA >$src2",
+                  [(set AccRegs:$dst, (load ADDRabsl:$src2))]>;  
+
+def LDAdp :  Group1<OpGrp1LDA, AddrModeGrp1DP,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "LDA <$src2",
+                  [(set AccRegs:$dst, (load ADDRdp:$src2))]>; 
+
+def LDAdpindir :  Group1<OpGrp1LDA, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "LDA (<$src2)",
+                  []>;  
+
+def LDAdpindirl :  Group1<OpGrp1LDA, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "LDA [<$src2]",
+                  []>;  
+
+def LDAabsix :  Group1<OpGrp1LDA, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "LDA |$src2,$src3",
+                  []>;   
+
+def LDAabsiy :  Group1<OpGrp1LDA, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "LDA |$src2,$src3",
+                  []>;  
+
+def LDAabsixl :  Group1<OpGrp1LDA, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "LDA >$src2,$src3",
+                  []>; 
+
+def LDAdpix :  Group1<OpGrp1LDA, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "LDA <$src2,$src3",
+                  []>;  
+
+def LDAdpiindirx :  Group1<OpGrp1LDA, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "LDA (<$src2,$src3)",
+                  []>; 
+
+def LDAdpindiriy :  Group1<OpGrp1LDA, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "LDA (<$src2),$src3",
+                  []>;
+
+def LDAdpindirliy :  Group1<OpGrp1LDA, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "LDA [<$src2],$src2",
+                  []>; 
+
+def LDAsr :  Group1<OpGrp1LDA, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "LDA <$src2,S",
+                  []>;  
+
+def LDAsrindir :  Group1<OpGrp1LDA, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "LDA (<$src2,S),$src3",
+                  []>;                       
+
+def ORAimm : Group1<OpGrp1ORA, AddrModeGrp1Imm,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16imm:$src2),
+                  "ORA #>$src2",
+                  [(set AccRegs:$dst, (or AccRegs:$src1, i16imm:$src2))]>;
+
+def ORAabs :  Group1<OpGrp1ORA, AddrModeGrp1Abs,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2),
+                  "ORA |$src2",
+                  [(set AccRegs:$dst, (or AccRegs:$src1, (load ADDRabs:$src2)))]>;   
+
+def ORAabsl :  Group1<OpGrp1ORA, AddrModeGrp1AbsLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2),
+                  "ORA >$src2",
+                  [(set AccRegs:$dst, (or AccRegs:$src1, (load ADDRabsl:$src2)))]>;  
+
+def ORAdp :  Group1<OpGrp1ORA, AddrModeGrp1DP,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ORA <$src2",
+                  [(set AccRegs:$dst, (or AccRegs:$src1, (load ADDRdp:$src2)))]>; 
+
+def ORAdpindir :  Group1<OpGrp1ORA, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ORA (<$src2)",
+                  []>;  
+
+def ORAdpindirl :  Group1<OpGrp1ORA, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ORA [<$src2]",
+                  []>;  
+
+def ORAabsix :  Group1<OpGrp1ORA, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "ORA |$src2,$src3",
+                  []>;   
+
+def ORAabsiy :  Group1<OpGrp1ORA, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "ORA |$src2,$src3",
+                  []>;  
+
+def ORAabsixl :  Group1<OpGrp1ORA, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "ORA >$src2,$src3",
+                  []>; 
+
+def ORAdpix :  Group1<OpGrp1ORA, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "ORA <$src2,$src3",
+                  []>;  
+
+def ORAdpiindirx :  Group1<OpGrp1ORA, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "ORA (<$src2,$src3)",
+                  []>; 
+
+def ORAdpindiriy :  Group1<OpGrp1ORA, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "ORA (<$src2),$src3",
+                  []>;
+
+def ORAdpindirliy :  Group1<OpGrp1ORA, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "ORA [<$src2],$src2",
+                  []>; 
+
+def ORAsr :  Group1<OpGrp1ORA, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "ORA <$src2,S",
+                  []>;  
+
+def ORAsrindir :  Group1<OpGrp1ORA, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "ORA (<$src2,S),$src3",
+                  []>;                        
+
+def SBCimm : Group1<OpGrp1SBC, AddrModeGrp1Imm,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16imm:$src2),
+                  "SBC #>$src2",
+                  [(set AccRegs:$dst, (sub AccRegs:$src1, i16imm:$src2))]>;
+
+def SBCabs :  Group1<OpGrp1SBC, AddrModeGrp1Abs,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2),
+                  "SBC |$src2",
+                  (set AccRegs:$dst, (sub AccRegs:$src1, (load ADDRabs:$src2)))>;   
+
+def SBCabsl :  Group1<OpGrp1SBC, AddrModeGrp1AbsLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2),
+                  "SBC >$src2",
+                  [(set AccRegs:$dst, (sub AccRegs:$src1, (load ADDRabsl:$src2)))]>;  
+
+def SBCdp :  Group1<OpGrp1SBC, AddrModeGrp1DP,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "SBC <$src2",
+                  [(set AccRegs:$dst, (sub AccRegs:$src1, (load ADDRdp:$src2)))]>; 
+
+def SBCdpindir :  Group1<OpGrp1SBC, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "SBC (<$src2)",
+                  []>;  
+
+def SBCdpindirl :  Group1<OpGrp1SBC, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "SBC [<$src2]",
+                  []>;  
+
+def SBCabsix :  Group1<OpGrp1SBC, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "SBC |$src2,$src3",
+                  []>;   
+
+def SBCabsiy :  Group1<OpGrp1SBC, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "SBC |$src2,$src3",
+                  []>;  
+
+def SBCabsixl :  Group1<OpGrp1SBC, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "SBC >$src2,$src3",
+                  []>; 
+
+def SBCdpix :  Group1<OpGrp1SBC, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "SBC <$src2,$src3",
+                  []>;  
+
+def SBCdpiindirx :  Group1<OpGrp1SBC, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "SBC (<$src2,$src3)",
+                  []>; 
+
+def SBCdpindiriy :  Group1<OpGrp1SBC, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "SBC (<$src2),$src3",
+                  []>;
+
+def SBCdpindirliy :  Group1<OpGrp1SBC, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "SBC [<$src2],$src2",
+                  []>; 
+
+def SBCsr :  Group1<OpGrp1SBC, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "SBC <$src2,S",
+                  []>;  
+
+def SBCsrindir :  Group1<OpGrp1SBC, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "SBC (<$src2,S),$src3",
+                  []>;  
+
+def STAabs :  Group1<OpGrp1STA, AddrModeGrp1Abs,
+                  (outs i16mem:$dst), (ins AccRegs:$src),
+                  "STA |$dst",
+                  [(store AccRegs:$src, ADDRabs:$dst)]>;   
+
+def STAabsl :  Group1<OpGrp1STA, AddrModeGrp1AbsLong,
+                  (outs i32mem:$dst), (ins AccRegs:$src),
+                  "STA >$dst",
+                  [(store AccRegs:$src, ADDRabsl:$dst)]>;  
+
+def STAdp :  Group1<OpGrp1STA, AddrModeGrp1DP,
+                  (outs i8mem:$dst), (ins AccRegs:$src),
+                  "STA <$dst",
+                  [(store AccRegs:$src, ADDRdp:$dst)]>; 
+
+def STAdpindir :  Group1<OpGrp1STA, AddrModeGrp1DPIndir,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "STA (<$src2)",
+                  []>;  
+
+def STAdpindirl :  Group1<OpGrp1STA, AddrModeGrp1DPIndirLong,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "STA [<$src2]",
+                  []>;  
+
+def STAabsix :  Group1<OpGrp1STA, AddrModeGrp1AbsIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "STA |$src2,$src3",
+                  []>;   
+
+def STAabsiy :  Group1<OpGrp1STA, AddrModeGrp1AbsIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i16mem:$src2, IndexYRegs:$src3),
+                  "STA |$src2,$src3",
+                  []>;  
+
+def STAabsixl :  Group1<OpGrp1STA, AddrModeGrp1AbsLongIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i32mem:$src2, IndexXRegs:$src3),
+                  "STA >$src2,$src3",
+                  []>; 
+
+def STAdpix :  Group1<OpGrp1STA, AddrModeGrp1DPIdxX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "STA <$src2,$src3",
+                  []>;  
+
+def STAdpiindirx :  Group1<OpGrp1STA, AddrModeGrp1DPIdxIndirX,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "STA (<$src2,$src3)",
+                  []>; 
+
+def STAdpindiriy :  Group1<OpGrp1STA, AddrModeGrp1DPIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "STA (<$src2),$src3",
+                  []>;
+
+def STAdpindirliy :  Group1<OpGrp1STA, AddrModeGrp1DPIndirLongIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "STA [<$src2],$src2",
+                  []>; 
+
+def STAsr :  Group1<OpGrp1STA, AddrModeGrp1StackRel,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2),
+                  "STA <$src2,S",
+                  []>;  
+
+def STAsrindir :  Group1<OpGrp1STA, AddrModeGrp1StackRelIndirIdxY,
+                  (outs AccRegs:$dst), (ins AccRegs:$src1, i8mem:$src2, IndexYRegs:$src3),
+                  "STA (<$src2,S),$src3",
+                  []>;   
+
+// Group #2 Instructions
+
+def ASLacc : Group2<OpGrp2ASL, AddrModeGrp2Acc,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "ASL $src",
+                  [(set AccRegs:$dst, (shl AccRegs:$src, (i8 1)))]>;
+                  
+def ASLabs : Group2<OpGrp2ASL, AddrModeGrp2Abs,
+                  (outs i16mem:$src), (ins i16mem:$src),
+                  "ASL |$src",
+                  [(store (shl (load ADDRabs:$src), (i8 1)), ADDRabs:$src)]>;
+                  
+def ASLdp : Group2<OpGrp2ASL, AddrModeGrp2DP,
+                  (outs i8mem:$src), (ins i8mem:$src),
+                  "ASL <$src",
+                  [(store (shl (load ADDRdp:$src), (i8 1)), ADDRdp:$src)]>;
+                  
+def ASLabsix : Group2<OpGrp2ASL, AddrModeGrp2AbsIdx,
+                  (outs i16mem:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "ASL |$src1,$src2",
+                  []>;
+                  
+def ASLdpix : Group2<OpGrp2ASL, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "ASL <$src1,$src2",
+                  []>;
+
+def DECacc : Group2<OpGrp2DEC, AddrModeGrp2Acc,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "DEC $src",
+                  [(set AccRegs:$dst, (sub AccRegs:$src, 1))]>;
+                  
+def DECabs : Group2<OpGrp2DEC, AddrModeGrp2Abs,
+                  (outs i16mem:$src), (ins i16mem:$src),
+                  "DEC |$src",
+                  [(store (sub (load ADDRabs:$src), 1), ADDRabs:$src)]>;
+                  
+def DECdp : Group2<OpGrp2DEC, AddrModeGrp2DP,
+                  (outs i8mem:$src), (ins i8mem:$src),
+                  "DEC <$src",
+                  [(store (sub (load ADDRdp:$src), 1), ADDRdp:$src)]>;
+                  
+def DECabsix : Group2<OpGrp2DEC, AddrModeGrp2AbsIdx,
+                  (outs i16mem:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "DEC |$src1,$src2",
+                  []>;
+                  
+def DECdpix : Group2<OpGrp2DEC, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "DEC <$src1,$src2",
+                  []>;
+
+def INCacc : Group2<OpGrp2INC, AddrModeGrp2Acc,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "INC $src",
+                  [(set AccRegs:$dst, (add AccRegs:$src, 1))]>;
+                  
+def INCabs : Group2<OpGrp2INC, AddrModeGrp2Abs,
+                  (outs i16mem:$src), (ins i16mem:$src),
+                  "INC |$src",
+                  [(store (add (load ADDRabs:$src), 1), ADDRabs:$src)]>;
+                  
+def INCdp : Group2<OpGrp2INC, AddrModeGrp2DP,
+                  (outs i8mem:$src), (ins i8mem:$src),
+                  "INC <$src",
+                  [(store (add (load ADDRdp:$src), 1), ADDRdp:$src)]>;
+                  
+def INCabsix : Group2<OpGrp2INC, AddrModeGrp2AbsIdx,
+                  (outs i16mem:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "INC |$src1,$src2",
+                  []>;
+                  
+def INCdpix : Group2<OpGrp2INC, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "INC <$src1,$src2",
+                  []>;
+
+def LDXimm : Group2<OpGrp2LDXY, AddrModeGrp2Imm,
+                  (outs IndexXRegs:$dst), (ins i16imm:$src),
+                  "LDX #$src",
+                  [(set IndexXRegs:$dst, i16imm:$src)]>;
+                  
+def LDXabs : Group2<OpGrp2LDXY, AddrModeGrp2Abs,
+                  (outs IndexXRegs:$dst), (ins i16mem:$src),
+                  "LDX |$src",
+                  [(set IndexXRegs:$dst, (load ADDRabs:$src))]>;
+                  
+def LDXdp : Group2<OpGrp2LDXY, AddrModeGrp2DP,
+                  (outs IndexXRegs:$dst), (ins i8mem:$src),
+                  "LDX <$src",
+                  [(set IndexXRegs:$dst, (load ADDRdp:$src))]>;
+                  
+def LDXabsiy : Group2<OpGrp2LDXY, AddrModeGrp2AbsIdx,
+                  (outs IndexXRegs:$dst), (ins i16mem:$src1, IndexYRegs:$src2),
+                  "LDX |$src1,$src2",
+                  []>;
+                  
+def LDXdpiy : Group2<OpGrp2LDXY, AddrModeGrp2DPIdx,
+                  (outs IndexXRegs:$dst), (ins i8mem:$src1, IndexYRegs:$src2),
+                  "LDX <$src1,$src2",
+                  []>;
+
+def LDYimm : Group2_Y<OpGrp2LDXY, AddrModeGrp2Imm,
+                  (outs IndexYRegs:$dst), (ins i16imm:$src),
+                  "LDY #$src",
+                  [(set IndexYRegs:$dst, i16imm:$src)]>;
+                  
+def LDYabs : Group2_Y<OpGrp2LDXY, AddrModeGrp2Abs,
+                  (outs IndexYRegs:$dst), (ins i16mem:$src),
+                  "LDY |$src",
+                  [(set IndexYRegs:$dst, (load ADDRabs:$src))]>;
+                  
+def LDYdp : Group2_Y<OpGrp2LDXY, AddrModeGrp2DP,
+                  (outs IndexYRegs:$dst), (ins i8mem:$src),
+                  "LDY <$src",
+                  [(set IndexYRegs:$dst, (load ADDRdp:$src))]>;
+                  
+def LDYabsix : Group2_Y<OpGrp2LDXY, AddrModeGrp2AbsIdx,
+                  (outs IndexYRegs:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "LDY |$src1,$src2",
+                  []>;
+                  
+def LDYdpix : Group2_Y<OpGrp2LDXY, AddrModeGrp2DPIdx,
+                  (outs IndexYRegs:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "LDY <$src1,$src2",
+                  []>;
+
+def LSRacc : Group2<OpGrp2LSR, AddrModeGrp2Acc,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "LSR $src",
+                  [(set AccRegs:$dst, (shr AccRegs:$src, (i8 1)))]>;
+                  
+def LSRabs : Group2<OpGrp2LSR, AddrModeGrp2Abs,
+                  (outs i16mem:$src), (ins i16mem:$src),
+                  "LSR |$src",
+                  [(store (shr (load ADDRabs:$src), (i8 1)), ADDRabs:$src)]>;
+                  
+def LSRdp : Group2<OpGrp2LSR, AddrModeGrp2DP,
+                  (outs i8mem:$src), (ins i8mem:$src),
+                  "LSR <$src",
+                  [(store (shr (load ADDRdp:$src), (i8 1)), ADDRdp:$src)]>;
+                  
+def LSRabsix : Group2<OpGrp2LSR, AddrModeGrp2AbsIdx,
+                  (outs i16mem:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "LSR |$src1,$src2",
+                  []>;
+                  
+def LSRdpix : Group2<OpGrp2LSR, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "LSR <$src1,$src2",
+                  []>;
+
+def ROLacc : Group2<OpGrp2ROL, AddrModeGrp2Acc,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "ROL $src",
+                  [(set AccRegs:$dst, (rotl AccRegs:$src, (i8 1)))]>;
+                  
+def ROLabs : Group2<OpGrp2ROL, AddrModeGrp2Abs,
+                  (outs i16mem:$src), (ins i16mem:$src),
+                  "ROL |$src",
+                  [(store (rotl (load ADDRabs:$src), (i8 1)), ADDRabs:$src)]>;
+                  
+def ROLdp : Group2<OpGrp2ROL, AddrModeGrp2DP,
+                  (outs i8mem:$src), (ins i8mem:$src),
+                  "ROL <$src",
+                  [(store (rotl (load ADDRdp:$src), (i8 1)), ADDRdp:$src)]>;
+                  
+def ROLabsix : Group2<OpGrp2ROL, AddrModeGrp2AbsIdx,
+                  (outs i16mem:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "ROL |$src1,$src2",
+                  []>;
+                  
+def ROLdpix : Group2<OpGrp2ROL, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "ROL <$src1,$src2",
+                  []>;
+
+def RORacc : Group2<OpGrp2ROR, AddrModeGrp2Acc,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "ROR $src",
+                  [(set AccRegs:$dst, (rotr AccRegs:$src, (i8 1)))]>;
+                  
+def RORabs : Group2<OpGrp2ROR, AddrModeGrp2Abs,
+                  (outs i16mem:$src), (ins i16mem:$src),
+                  "ROR |$src",
+                  [(store (rotr (load ADDRabs:$src), (i8 1)), ADDRabs:$src)]>;
+                  
+def RORdp : Group2<OpGrp2ROR, AddrModeGrp2DP,
+                  (outs i8mem:$src), (ins i8mem:$src),
+                  "ROR <$src",
+                  [(store (rotr (load ADDRdp:$src), (i8 1)), ADDRdp:$src)]>;
+                  
+def RORabsix : Group2<OpGrp2ROR, AddrModeGrp2AbsIdx,
+                  (outs i16mem:$dst), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "ROR |$src1,$src2",
+                  []>;
+                  
+def RORdpix : Group2<OpGrp2ROR, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "ROR <$src1,$src2",
+                  []>;
+
+def STXabs : Group2<OpGrp2STXY, AddrModeGrp2Abs,
+                  (outs i16mem:$dst), (ins IndexXRegs:$src),
+                  "STX |$dst",
+                  [(store IndexXRegs:$src, ADDRabs:$dst)]>;
+                  
+def STXdp : Group2<OpGrp2STXY, AddrModeGrp2DP,
+                  (outs i8mem:$dst), (ins IndexXRegs:$src),
+                  "STX <$dst",
+                  [(store IndexXRegs:$src, ADDRdp:$dst)]>;
+                  
+def STXdpiy : Group2<OpGrp2STXY, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins IndexXRegs:$src1, IndexYRegs:$src2),
+                  "STX <$dst,$src2",
+                  []>;
+
+def STYabs : Group2_Y<OpGrp2STXY, AddrModeGrp2Abs,
+                  (outs i16mem:$dst), (ins IndexYRegs:$src),
+                  "STY |$dst",
+                  [(store IndexYRegs:$src, ADDRabs:$dst)]>;
+                  
+def STYdp : Group2_Y<OpGrp2STXY, AddrModeGrp2DP,
+                  (outs i8mem:$dst), (ins IndexYRegs:$src),
+                  "STY <$dst",
+                  [(store IndexYRegs:$src, ADDRdp:$dst)]>;
+                  
+def STYdpix : Group2_Y<OpGrp2STXY, AddrModeGrp2DPIdx,
+                  (outs i16mem:$dst), (ins IndexYRegs:$src1, IndexXRegs:$src2),
+                  "STY <$dst,$src2",
+                  []>;
+
+                  
+                  
+// Group #3 Instructions
+
+def BCC : Group3<OpGrp3BCC,
+                  (outs ), (ins i8mem:$src),
+                  "BCC <$src",
+                  []>;
+
+def BCS : Group3<OpGrp3BCS,
+                  (outs ), (ins i8mem:$src),
+                  "BCS <$src",
+                  []>;
+
+def BEQ : Group3<OpGrp3BEQ,
+                  (outs ), (ins i8mem:$src),
+                  "BEQ <$src",
+                  []>;
+
+def BITimm : Group3<OpGrp3BITImm,
+                  (outs ), (ins AccRegs:$src1, i16imm:$src2),
+                  "BIT #>$src2",
+                  []>;
+                  
+def BITabs : Group3<OpGrp3BITAbs,
+                  (outs ), (ins AccRegs:$src1, i16mem:$src2),
+                  "BIT |$src2",
+                  []>;
+                  
+def BITdp : Group3<OpGrp3BITDp,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2),
+                  "BIT <$src",
+                  []>;
+                  
+def BITabsix : Group3<OpGrp3BITAbsi,
+                  (BIT ), (ins AccRegs:$src1, i16mem:$src2, IndexXRegs:$src3),
+                  "ASL |$src2,$src3",
+                  []>;
+                  
+def BITdpix : Group3<OpGrp3BITDpi,
+                  (outs ), (ins AccRegs:$src1, i8mem:$src2, IndexXRegs:$src3),
+                  "BIT <$src2,$src3",
+                  []>;
+
+def BMI : Group3<OpGrp3BMI,
+                  (outs ), (ins i8mem:$src),
+                  "BMI <$src",
+                  []>;
+
+def BNE : Group3<OpGrp3BNE,
+                  (outs ), (ins i8mem:$src),
+                  "BNE <$src",
+                  []>;
+
+def BPL : Group3<OpGrp3BPL,
+                  (outs ), (ins i8mem:$src),
+                  "BPL <$src",
+                  []>;
+
+def BRA : Group3<OpGrp3BRA,
+                  (outs ), (ins i8mem:$src),
+                  "BRA <$src",
+                  []>;
+
+def BRK : Group3<OpGrp3BRK,
+                  (outs ), (ins i8imm:$src),
+                  "BRK <$src",
+                  []>;
+
+def BRL : Group3<OpGrp3BRL,
+                  (outs ), (ins i16mem:$src),
+                  "BRL |$src",
+                  []>;
+
+def BVC : Group3<OpGrp3BVC,
+                  (outs ), (ins i8mem:$src),
+                  "BVC <$src",
+                  []>;
+
+def BVS : Group3<OpGrp3BVS,
+                  (outs ), (ins i8mem:$src),
+                  "BVS <$src",
+                  []>;
+
+def CLC : Group3<OpGrp3CLC,
+                  (outs ), (ins ),
+                  "CLC",
+                  []>;
+
+def CLD : Group3<OpGrp3CLD,
+                  (outs ), (ins ),
+                  "CLD",
+                  []>;
+
+def CLI : Group3<OpGrp3CLI,
+                  (outs ), (ins ),
+                  "CLI",
+                  []>;
+
+def CLV : Group3<OpGrp3CLV,
+                  (outs ), (ins ),
+                  "CLV",
+                  []>;
+
+def COP : Group3<OpGrp3COP,
+                  (outs ), (ins i8imm:$src),
+                  "COP <$src",
+                  []>;
+
+def CPXimm : Group3<OpGrp3CPXimm,
+                  (outs ), (ins IndexXRegs:$src1, i16imm:$src2),
+                  "CPX #$src2",
+                  []>;
+
+def CPXabs :  Group3<OpGrp3CPXabs,
+                  (outs ), (ins IndexXRegs:$src1, i16mem:$src2),
+                  "CPX |$src2",
+                  []>;    
+
+def CPXdp :  Group3<OpGrp3CPXdp,
+                  (outs ), (ins IndexXRegs:$src1, i8mem:$src2),
+                  "CPX <$src2",
+                  []>; 
+
+def CPYimm : Group3<OpGrp3CPYimm,
+                  (outs ), (ins IndexYRegs:$src1, i16imm:$src2),
+                  "CPY #$src2",
+                  []>;
+
+def CPYabs :  Group3<OpGrp3CPYabs,
+                  (outs ), (ins IndexYRegs:$src1, i16mem:$src2),
+                  "CPY |$src2",
+                  []>;    
+
+def CPYdp :  Group3<OpGrp3CPYdp,
+                  (outs ), (ins IndexYRegs:$src1, i8mem:$src2),
+                  "CPY <$src2",
+                  []>;  
+
+def DEX :  Group3<OpGrp3DEX,
+                  (outs IndexXRegs:$dst), (ins IndexXRegs:$src),
+                  "DEX",
+                  [(set IndexXRegs:$dst, (sub IndexXRegs:$src, 1))]>; 
+
+def DEY :  Group3<OpGrp3DEY,
+                  (outs IndexYRegs:$dst), (ins IndexYRegs:$src),
+                  "DEY",
+                  [(set IndexYRegs:$dst, (sub IndexYRegs:$src, 1))]>; 
+
+def INX :  Group3<OpGrp3INX,
+                  (outs IndexXRegs:$dst), (ins IndexXRegs:$src),
+                  "INX",
+                  [(set IndexXRegs:$dst, (add IndexXRegs:$src, 1))]>; 
+
+def INY :  Group3<OpGrp3INY,
+                  (outs IndexYRegs:$dst), (ins IndexYRegs:$src),
+                  "INY",
+                  [(set IndexYRegs:$dst, (add IndexYRegs:$src, 1))]>; 
+
+def JMPabs : Group3<OpGrp3JMPabs,
+                  (outs ), (ins i16mem:$src),
+                  "JMP |$src",
+                  []>;
+
+def JMPindir : Group3<OpGrp3JMPindir,
+                  (outs ), (ins i16mem:$src),
+                  "JMP (|$src)",
+                  []>;
+
+def JMPindiri : Group3<OpGrp3JMPindiri,
+                  (outs ), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "JMP (|$src1,$src2)",
+                  []>;
+
+def JMLabs : Group3<OpGrp3JMLabs,
+                  (outs ), (ins i32mem:$src),
+                  "JML >$src",
+                  []>;
+
+def JMLindirl : Group3<OpGrp3JMLindir,
+                  (outs ), (ins i32mem:$src),
+                  "JML [>$src]",
+                  []>;
+
+def JSL : Group3<OpGrp3JSL,
+                  (outs ), (ins i32mem:$src),
+                  "JSL >$src",
+                  []>;
+
+def JSRabs : Group3<OpGrp3JSRabs,
+                  (outs ), (ins i16mem:$src),
+                  "JSR |$src",
+                  []>;
+
+def JSRindiri : Group3<OpGrp3JSRindiri,
+                  (outs ), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "JSR (|$src1,$src2)",
+                  []>;
+
+def MVN : Group3<OpGrp3MVN,
+                  (outs ), (ins i8mem:$src1, i8mem:$src2, AccRegs:$src3, IndexXRegs:$src4, IndexYRegs:$src5),
+                  "MVN <$src1,<$src2",
+                  []>;
+
+def MVP : Group3<OpGrp3MVP,
+                  (outs ), (ins i8mem:$src1, i8mem:$src2, AccRegs:$src3, IndexXRegs:$src4, IndexYRegs:$src5),
+                  "MVP <$src1,<$src2",
+                  []>;
+
+def NOP : Group3<OpGrp3NOP,
+                  (outs ), (ins ),
+                  "NOP",
+                  []>;
+
+def PEA : Group3<OpGrp3PEA,
+                  (outs ), (ins i16imm:$src),
+                  "PEA |$src",
+                  []>;
+
+def PEI : Group3<OpGrp3PEI,
+                  (outs ), (ins i8imm:$src),
+                  "PEI (<$src)",
+                  []>;
+
+def PER : Group3<OpGrp3PER,
+                  (outs ), (ins i16imm:$src),
+                  "PER |$src",
+                  []>;
+
+def PHA : Group3<OpGrp3PHA,
+                  (outs ), (ins AccRegs:$src),
+                  "PHA",
+                  []>;
+
+def PHB : Group3<OpGrp3PHB,
+                  (outs ), (ins ),
+                  "PHB",
+                  []>;
+
+def PHD : Group3<OpGrp3PHD,
+                  (outs ), (ins ),
+                  "PHD",
+                  []>;
+
+def PHK : Group3<OpGrp3PHK,
+                  (outs ), (ins ),
+                  "PHK",
+                  []>;
+
+def PHP : Group3<OpGrp3PHP,
+                  (outs ), (ins ),
+                  "PHP",
+                  []>;
+
+def PHX : Group3<OpGrp3PHX,
+                  (outs ), (ins IndexXRegs:$src),
+                  "PHX",
+                  []>;
+
+def PHY : Group3<OpGrp3PHY,
+                  (outs ), (ins IndexYRegs:$src),
+                  "PHY",
+                  []>;
+
+def PLA : Group3<OpGrp3PLA,
+                  (outs AccRegs:$dst), (ins ),
+                  "PLA",
+                  []>;
+
+def PLB : Group3<OpGrp3PLB,
+                  (outs ), (ins ),
+                  "PLB",
+                  []>;
+
+def PLD : Group3<OpGrp3PLD,
+                  (outs ), (ins ),
+                  "PLD",
+                  []>;
+
+def PLP : Group3<OpGrp3PLP,
+                  (outs ), (ins ),
+                  "PLP",
+                  []>;
+
+def PLX : Group3<OpGrp3PLX,
+                  (outs IndexXRegs:$dst), (ins ),
+                  "PLX",
+                  []>;
+
+def PLY : Group3<OpGrp3PLY,
+                  (outs IndexYRegs:$dst), (ins ),
+                  "PLY",
+                  []>;
+
+def REP : Group3<OpGrp3REP,
+                  (outs ), (ins i8imm:$src),
+                  "REP #$src",
+                  []>;
+
+def RTI : Group3<OpGrp3RTI,
+                  (outs ), (ins ),
+                  "RTI",
+                  []>;
+
+def RTL : Group3<OpGrp3RTL,
+                  (outs ), (ins ),
+                  "RTL",
+                  []>;
+
+def RTS : Group3<OpGrp3RTS,
+                  (outs ), (ins ),
+                  "RTS",
+                  []>;
+
+def SEC : Group3<OpGrp3SEC,
+                  (outs ), (ins ),
+                  "SEC",
+                  []>;
+
+def SED : Group3<OpGrp3SED,
+                  (outs ), (ins ),
+                  "SED",
+                  []>;
+
+def SEI : Group3<OpGrp3SEI,
+                  (outs ), (ins ),
+                  "SEI",
+                  []>;
+
+def SEP : Group3<OpGrp3SEP,
+                  (outs ), (ins i8imm:$src),
+                  "SEP #$src",
+                  []>;
+
+def STP : Group3<OpGrp3STP,
+                  (outs ), (ins ),
+                  "STP",
+                  []>;
+
+def STZabs :  Group3<OpGrp3STZabs,
+                  (outs i16mem:$dst), (ins ),
+                  "STZ |$dst",
+                  [(store 0, ADDRabs:$dst)]>;    
+
+def STZdp :  Group3<OpGrp3STZdp,
+                  (outs i8mem:$dst), (ins ),
+                  "STZ <$dst",
+                  [(store 0, ADDRdp:$dst)]>; 
+
+def STZabsi :  Group3<OpGrp3STZabsi,
+                  (outs ), (ins i16mem:$src1, IndexXRegs:$src2),
+                  "STZ |$src1,$src2",
+                  []>;    
+
+def STZdpi :  Group3<OpGrp3STZdpi,
+                  (outs ), (ins i8mem:$src1, IndexXRegs:$src2),
+                  "STZ <$src,$src2",
+                  []>;  
+
+def TAX :  Group3<OpGrp3TAX,
+                  (outs IndexXRegs:$dst), (ins AccRegs:$src),
+                  "TAX",
+                  [(set IndexXRegs:$dst, AccRegs:$src)]>; 
+
+def TAY :  Group3<OpGrp3TAY,
+                  (outs IndexYRegs:$dst), (ins AccRegs:$src),
+                  "TAY",
+                  [(set IndexYRegs:$dst, AccRegs:$src)]>; 
+
+def TCB :  Group3<OpGrp3TCB,
+                  (outs DirectPageRegs:$dst), (ins AccRegs:$src),
+                  "TCB",
+                  [(set DirectPageRegs:$dst, AccRegs:$src)]>; 
+
+def TCS :  Group3<OpGrp3TCS,
+                  (outs StackPointerRegs:$dst), (ins AccRegs:$src),
+                  "TCS",
+                  [(set StackPointerRegs:$dst, AccRegs:$src)]>; 
+
+def TDC :  Group3<OpGrp3TDC,
+                  (outs AccRegs:$dst), (ins DirectPageRegs:$src),
+                  "TDC",
+                  [(set AccRegs:$dst, DirectPageRegs:$src)]>; 
+
+def TRBabs :  Group3<OpGrp3TRBabs,
+                  (outs ), (ins i16mem:$src1, AccRegs:$src2),
+                  "TRB |$src1",
+                  []>; 
+
+def TRBdp :  Group3<OpGrp3TRBdp,
+                  (outs ), (ins i8mem:$src1, AccRegs:$src2),
+                  "TRB <$src1",
+                  []>; 
+
+def TSBabs :  Group3<OpGrp3TSBabs,
+                  (outs ), (ins i16mem:$src1, AccRegs:$src2),
+                  "TSB |$src1",
+                  []>; 
+
+def TSBdp :  Group3<OpGrp3TSBdp,
+                  (outs ), (ins i8mem:$src1, AccRegs:$src2),
+                  "TSB <$src1",
+                  []>; 
+
+def TSC :  Group3<OpGrp3TSC,
+                  (outs AccRegs:$dst), (ins StackPointerRegs:$src),
+                  "TSC",
+                  [(set AccRegs:$dst, StackPointerRegs:$src)]>; 
+
+def TSX :  Group3<OpGrp3TSX,
+                  (outs IndexXRegs:$dst), (ins StackPointerRegs:$src),
+                  "TSX",
+                  [(set IndexXRegs:$dst, StackPointerRegs:$src)]>; 
+
+def TXA :  Group3<OpGrp3TXA,
+                  (outs AccRegs:$dst), (ins IndexXRegs:$src),
+                  "TXA",
+                  [(set AccRegs:$dst, IndexXRegs:$src)]>; 
+
+def TXS :  Group3<OpGrp3TXS,
+                  (outs StackPointerRegs:$dst), (ins IndexXRegs:$src),
+                  "TXS",
+                  [(set StackPointerRegs:$dst, IndexXRegs:$src)]>; 
+
+def TXY :  Group3<OpGrp3TXY,
+                  (outs IndexYRegs:$dst), (ins IndexXRegs:$src),
+                  "TXY",
+                  [(set IndexYRegs:$dst, IndexXRegs:$src)]>; 
+
+def TYA :  Group3<OpGrp3TYA,
+                  (outs AccRegs:$dst), (ins IndexYRegs:$src),
+                  "TYA",
+                  [(set AccRegs:$dst, IndexYRegs:$src)]>; 
+
+def TYX :  Group3<OpGrp3TYX,
+                  (outs IndexXRegs:$dst), (ins IndexYRegs:$src),
+                  "TYX",
+                  [(set IndexXRegs:$dst, IndexYRegs:$src)]>; 
+
+def WAI :  Group3<OpGrp3WAI,
+                  (outs ), (ins ),
+                  "WAI",
+                  []>; 
+
+def WDM :  Group3<OpGrp3WDM,
+                  (outs ), (ins i8imm:$src),
+                  "WDM $src",
+                  []>; 
+
+def XBA :  Group3<OpGrp3XBA,
+                  (outs AccRegs:$dst), (ins AccRegs:$src),
+                  "XBA",
+                  []>; 
+
+def XCE :  Group3<OpGrp3XCE,
+                  (outs ), (ins ),
+                  "XCE",
+                  []>; 
+
+
+//===----------------------------------------------------------------------===//
+// Non-Instruction Patterns
+//===----------------------------------------------------------------------===//
+
diff --git a/lib/Target/WDC65816/WDC65816TargetMachine.cpp b/lib/Target/WDC65816/WDC65816TargetMachine.cpp
index afa61834..503f6245 100644
--- a/lib/Target/WDC65816/WDC65816TargetMachine.cpp
+++ b/lib/Target/WDC65816/WDC65816TargetMachine.cpp
@@ -31,10 +31,10 @@ WDC65816TargetMachine::WDC65816TargetMachine(const Target &T, StringRef TT,
                                        Reloc::Model RM, CodeModel::Model CM,
                                        CodeGenOpt::Level OL)
 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-DL(Subtarget.getDataLayout()),
-InstrInfo(Subtarget),
+DL("e-p:32:8:8-i16:8:8-f32:8:8-f68:8:8-n16"),
+InstrInfo(),
 TLInfo(*this), TSInfo(*this),
-FrameLowering(Subtarget) {
+FrameLowering() {
     initAsmInfo();
 }