mirror of
https://github.com/jeremysrand/llvm-65816.git
synced 2024-09-30 01:56:06 +00:00
More work to get a basic WDC65816 infrastructure in and compiling.
This commit is contained in:
parent
036df005af
commit
91e7016b1f
@ -12,7 +12,10 @@ LIBRARYNAME = LLVMWDC65816CodeGen
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TARGET = WDC65816
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES =
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BUILT_SOURCES = WDC65816GenRegisterInfo.inc WDC65816GenInstrInfo.inc \
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WDC65816GenAsmWriter.inc WDC65816GenDAGISel.inc \
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WDC65816GenSubtargetInfo.inc WDC65816GenCallingConv.inc \
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WDC65816GenCodeEmitter.inc
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# DIRS = InstPrinter Disassembler AsmParser TargetInfo MCTargetDesc
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@ -24,7 +24,6 @@ namespace llvm {
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class formatted_raw_ostream;
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FunctionPass *createWDC65816ISelDag(WDC65816TargetMachine &TM);
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FunctionPass *createWDC65816DelaySlotFillerPass(TargetMachine &TM);
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} // end namespace llvm;
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253
lib/Target/WDC65816/WDC65816FrameLowering.cpp
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253
lib/Target/WDC65816/WDC65816FrameLowering.cpp
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@ -0,0 +1,253 @@
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//===-- WDC65816FrameLowering.cpp - WDC65816 Frame Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the WDC65816 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "WDC65816FrameLowering.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#if 0 // JSR TODO - Do I need any of this?
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static cl::opt<bool>
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DisableLeafProc("disable-sparc-leaf-proc",
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cl::init(false),
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cl::desc("Disable Sparc leaf procedure optimization."),
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cl::Hidden);
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void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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int NumBytes,
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unsigned ADDrr,
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unsigned ADDri) const {
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DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
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if (NumBytes >= -4096 && NumBytes < 4096) {
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BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
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.addReg(SP::O6).addImm(NumBytes);
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return;
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}
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// Emit this the hard way. This clobbers G1 which we always know is
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// available here.
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if (NumBytes >= 0) {
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// Emit nonnegative numbers with sethi + or.
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// sethi %hi(NumBytes), %g1
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// or %g1, %lo(NumBytes), %g1
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// add %sp, %g1, %sp
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HI22(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
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.addReg(SP::G1).addImm(LO10(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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return ;
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}
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// Emit negative numbers with sethi + xor.
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// sethi %hix(NumBytes), %g1
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// xor %g1, %lox(NumBytes), %g1
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// add %sp, %g1, %sp
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HIX22(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
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.addReg(SP::G1).addImm(LOX10(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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}
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void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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unsigned SAVEri = SP::SAVEri;
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unsigned SAVErr = SP::SAVErr;
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if (FuncInfo->isLeafProc()) {
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if (NumBytes == 0)
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return;
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SAVEri = SP::ADDri;
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SAVErr = SP::ADDrr;
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}
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NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
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emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(SP::PROLOG_LABEL)).addSym(FrameLabel);
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unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
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// Emit ".cfi_def_cfa_register 30".
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MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
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regFP));
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// Emit ".cfi_window_save".
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MMI.addFrameInst(MCCFIInstruction::createWindowSave(FrameLabel));
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unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
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unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
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// Emit ".cfi_register 15, 31".
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MMI.addFrameInst(MCCFIInstruction::createRegister(FrameLabel,
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regOutRA,
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regInRA));
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}
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void SparcFrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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MachineInstr &MI = *I;
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int Size = MI.getOperand(0).getImm();
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
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}
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MBB.erase(I);
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}
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void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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assert(MBBI->getOpcode() == SP::RETL &&
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"Can only put epilog before 'retl' instruction!");
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if (!FuncInfo->isLeafProc()) {
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BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
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.addReg(SP::G0);
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return;
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}
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int NumBytes = (int) MFI->getStackSize();
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if (NumBytes == 0)
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return;
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NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
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emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
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}
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bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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// Reserve call frame if there are no variable sized objects on the stack.
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
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}
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static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
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{
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
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if (MRI->isPhysRegUsed(reg))
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return false;
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for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
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if (MRI->isPhysRegUsed(reg))
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return false;
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return true;
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}
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bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
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{
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return !(MFI->hasCalls() // has calls
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|| MRI.isPhysRegUsed(SP::L0) // Too many registers needed
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|| MRI.isPhysRegUsed(SP::O6) // %SP is used
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|| hasFP(MF)); // need %FP
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}
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void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Remap %i[0-7] to %o[0-7].
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
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if (!MRI.isPhysRegUsed(reg))
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continue;
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unsigned mapped_reg = (reg - SP::I0 + SP::O0);
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assert(!MRI.isPhysRegUsed(mapped_reg));
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// Replace I register with O register.
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MRI.replaceRegWith(reg, mapped_reg);
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// Mark the reg unused.
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MRI.setPhysRegUnused(reg);
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}
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// Rewrite MBB's Live-ins.
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
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if (!MBB->isLiveIn(reg))
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continue;
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MBB->removeLiveIn(reg);
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MBB->addLiveIn(reg - SP::I0 + SP::O0);
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}
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}
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assert(verifyLeafProcRegUse(&MRI));
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#ifdef XDEBUG
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MF.verify(0, "After LeafProc Remapping");
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#endif
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}
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void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
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(MachineFunction &MF, RegScavenger *RS) const {
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if (!DisableLeafProc && isLeafProc(MF)) {
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SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
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MFI->setLeafProc(true);
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remapRegsForLeafProc(MF);
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}
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}
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#endif
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59
lib/Target/WDC65816/WDC65816FrameLowering.h
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59
lib/Target/WDC65816/WDC65816FrameLowering.h
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@ -0,0 +1,59 @@
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//===-- WDC65816FrameLowering.h - Define frame lowering for Sparc --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef WDC65816_FRAMEINFO_H
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#define WDC65816_FRAMEINFO_H
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#include "WDC65816.h"
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#include "llvm/Target/TargetFrameLowering.h"
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namespace llvm {
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class WDC65816FrameLowering : public TargetFrameLowering {
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public:
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explicit WDC65816FrameLowering(void)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, 0) {}
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#if 0 // JSR TODO - do I need any of this?
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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bool hasReservedCallFrame(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS = NULL) const;
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private:
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// Remap input registers to output registers for leaf procedure.
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void remapRegsForLeafProc(MachineFunction &MF) const;
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// Returns true if MF is a leaf procedure.
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bool isLeafProc(MachineFunction &MF) const;
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// Emits code for adjusting SP in function prologue/epilogue.
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void emitSPAdjustment(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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int NumBytes, unsigned ADDrr, unsigned ADDri) const;
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#endif
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};
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} // End llvm namespace
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#endif
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0
lib/Target/WDC65816/WDC65816ISelLowering.h
Normal file
0
lib/Target/WDC65816/WDC65816ISelLowering.h
Normal file
232
lib/Target/WDC65816/WDC65816InstrFormats.td
Normal file
232
lib/Target/WDC65816/WDC65816InstrFormats.td
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//===- WDCInstrFormats.td - WDC 65816 Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class InstWDC<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
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field bits<8> Inst;
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let Namespace = "WDC";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// Group #1 instructions in the WDC 65816
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//===----------------------------------------------------------------------===//
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class OpGrp1<bits<3> val> {
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bits<3> Value = val;
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}
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def OpGrp1ADC : OpGrp1<3>;
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def OpGrp1AND : OpGrp1<1>;
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def OpGrp1CMP : OpGrp1<6>;
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def OpGrp1EOR : OpGrp1<2>;
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def OpGrp1LDA : OpGrp1<5>;
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def OpGrp1ORA : OpGrp1<0>;
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def OpGrp1SBC : OpGrp1<7>;
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def OpGrp1STA : OpGrp1<4>;
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class AddrModeGrp1<bits<5> val> {
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bits<5> Value = val;
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}
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def AddrModeGrp1Imm : AddrModeGrp1<9>;
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def AddrModeGrp1DP : AddrModeGrp1<5>;
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def AddrModeGrp1Abs : AddrModeGrp1<13>;
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def AddrModeGrp1DPIdxX : AddrModeGrp1<21>;
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def AddrModeGrp1AbsIdxX : AddrModeGrp1<29>;
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def AddrModeGrp1AbsIdxY : AddrModeGrp1<25>;
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def AddrModeGrp1DPIdxIndirX : AddrModeGrp1<1>;
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def AddrModeGrp1DPIndirIdxY : AddrModeGrp1<17>;
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def AddrModeGrp1DPIndir : AddrModeGrp1<18>;
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def AddrModeGrp1DPIndirLongIndY : AddrModeGrp1<23>;
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def AddrModeGrp1DPIndirLong : AddrModeGrp1<7>;
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def AddrModeGrp1AbsLong : AddrModeGrp1<15>;
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def AddrModeGrp1AbsLongIdxX : AddrModeGrp1<31>;
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def AddrModeGrp1StackRel : AddrModeGrp1<3>;
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def AddrModeGrp1StackRelIndirIdxY : AddrModeGrp1<19>;
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// Group 1 instructions
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class Group1<OpGrp1 opVal, AddrModeGrp1 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstWDC<outs, ins, asmstr, pattern> {
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OpGrp1 op = opVal;
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AddrModeGrp1 addrMode = addrModeVal;
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let Inst{7-5} = op.Value;
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let Inst{4-0} = addrMode.Value;
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}
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//===----------------------------------------------------------------------===//
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// Group #2 instructions in the WDC 65816
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//===----------------------------------------------------------------------===//
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class OpGrp2<bits<3> val> {
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bits<3> Value = val;
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}
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def OpGrp2ASL : OpGrp2<0>;
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def OpGrp2DEC : OpGrp2<6>;
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def OpGrp2INC : OpGrp2<7>;
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def OpGrp2LSR : OpGrp2<2>;
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def OpGrp2ROL : OpGrp2<1>;
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def OpGrp2ROR : OpGrp2<3>;
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def OpGrp2STXY : OpGrp2<4>;
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def OpGrp2LDXY : OpGrp2<5>;
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class AddrModeGrp2<bits<3> val> {
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bits<3> Value = val;
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}
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def AddrModeGrp2Acc : AddrModeGrp2<2>;
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def AddrModeGrp2DP : AddrModeGrp2<1>;
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def AddrModeGrp2Abs : AddrModeGrp2<3>;
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def AddrModeGrp2DPIdx : AddrModeGrp2<5>;
|
||||
def AddrModeGrp2AbsIdx : AddrModeGrp2<7>;
|
||||
def AddrModeGrp2Imm : AddrModeGrp2<0>;
|
||||
|
||||
// Group 2 instructions
|
||||
class Group2<OpGrp2 opVal, AddrModeGrp2 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstWDC<outs, ins, asmstr, pattern> {
|
||||
OpGrp2 op = opVal;
|
||||
AddrModeGrp2 addrMode = addrModeVal;
|
||||
|
||||
let Inst{7-5} = op.Value;
|
||||
let Inst{4-2} = addrMode.Value;
|
||||
let Inst{1-0} = 2;
|
||||
}
|
||||
|
||||
|
||||
// Group 2 Y instructions
|
||||
class Group2_Y<OpGrp2 opVal, AddrModeGrp2 addrModeVal, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: Group2<opVal, addrModeVal, outs, ins, asmstr, pattern> {
|
||||
OpGrp2 op = opVal;
|
||||
AddrModeGrp2 addrMode = addrModeVal;
|
||||
|
||||
let Inst{7-5} = op.Value;
|
||||
let Inst{4-2} = addrMode.Value;
|
||||
let Inst{1-0} = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Group #3 instructions in the WDC 65816
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class OpGrp3<bits<8> val> {
|
||||
bits<8> Value = val;
|
||||
}
|
||||
|
||||
|
||||
def OpGrp3BCC : OpGrp3<0x90>;
|
||||
def OpGrp3BCS : OpGrp3<0xB0>;
|
||||
def OpGrp3BEQ : OpGrp3<0xF0>;
|
||||
def OpGrp3BITImm : OpGrp3<0x89>;
|
||||
def OpGrp3BITAbs : OpGrp3<0x2C>;
|
||||
def OpGrp3BITDp : OpGrp3<0x24>;
|
||||
def OpGrp3BITAbsi : OpGrp3<0x3C>;
|
||||
def OpGrp3BITDpi : OpGrp3<0x34>;
|
||||
def OpGrp3BMI : OpGrp3<0x30>;
|
||||
def OpGrp3BNE : OpGrp3<0xD0>;
|
||||
def OpGrp3BPL : OpGrp3<0x10>;
|
||||
def OpGrp3BRA : OpGrp3<0x80>;
|
||||
def OpGrp3BRK : OpGrp3<0x00>;
|
||||
def OpGrp3BRL : OpGrp3<0x82>;
|
||||
def OpGrp3BVC : OpGrp3<0x50>;
|
||||
def OpGrp3BVS : OpGrp3<0x70>;
|
||||
def OpGrp3CLC : OpGrp3<0x18>;
|
||||
def OpGrp3CLD : OpGrp3<0xD8>;
|
||||
def OpGrp3CLI : OpGrp3<0x58>;
|
||||
def OpGrp3CLV : OpGrp3<0xB8>;
|
||||
def OpGrp3COP : OpGrp3<0x02>;
|
||||
def OpGrp3CPXimm : OpGrp3<0xE0>;
|
||||
def OpGrp3CPXabs : OpGrp3<0xEC>;
|
||||
def OpGrp3CPXdp : OpGrp3<0xE4>;
|
||||
def OpGrp3CPYimm : OpGrp3<0xC0>;
|
||||
def OpGrp3CPYabs : OpGrp3<0xCC>;
|
||||
def OpGrp3CPYdp : OpGrp3<0xC4>;
|
||||
def OpGrp3DEX : OpGrp3<0xCA>;
|
||||
def OpGrp3DEY : OpGrp3<0x88>;
|
||||
def OpGrp3INX : OpGrp3<0xE8>;
|
||||
def OpGrp3INY : OpGrp3<0xC8>;
|
||||
def OpGrp3JMPabs : OpGrp3<0x4C>;
|
||||
def OpGrp3JMPindir : OpGrp3<0x6C>;
|
||||
def OpGrp3JMPindiri : OpGrp3<0x7C>;
|
||||
def OpGrp3JMLabs : OpGrp3<0x5C>;
|
||||
def OpGrp3JMLindir : OpGrp3<0xDC>;
|
||||
def OpGrp3JSL : OpGrp3<0x22>;
|
||||
def OpGrp3JSRabs : OpGrp3<0x20>;
|
||||
def OpGrp3JSRindiri : OpGrp3<0xFC>;
|
||||
def OpGrp3MVN : OpGrp3<0x54>;
|
||||
def OpGrp3MVP : OpGrp3<0x44>;
|
||||
def OpGrp3NOP : OpGrp3<0xEA>;
|
||||
def OpGrp3PEA : OpGrp3<0xF4>;
|
||||
def OpGrp3PEI : OpGrp3<0xD4>;
|
||||
def OpGrp3PER : OpGrp3<0x62>;
|
||||
def OpGrp3PHA : OpGrp3<0x48>;
|
||||
def OpGrp3PHB : OpGrp3<0x8B>;
|
||||
def OpGrp3PHD : OpGrp3<0x0B>;
|
||||
def OpGrp3PHK : OpGrp3<0x4B>;
|
||||
def OpGrp3PHP : OpGrp3<0x08>;
|
||||
def OpGrp3PHX : OpGrp3<0xDA>;
|
||||
def OpGrp3PHY : OpGrp3<0x5A>;
|
||||
def OpGrp3PLA : OpGrp3<0x68>;
|
||||
def OpGrp3PLB : OpGrp3<0xAB>;
|
||||
def OpGrp3PLD : OpGrp3<0x2B>;
|
||||
def OpGrp3PLP : OpGrp3<0x28>;
|
||||
def OpGrp3PLX : OpGrp3<0xFA>;
|
||||
def OpGrp3PLY : OpGrp3<0x7A>;
|
||||
def OpGrp3REP : OpGrp3<0xC2>;
|
||||
def OpGrp3RTI : OpGrp3<0x40>;
|
||||
def OpGrp3RTL : OpGrp3<0x6B>;
|
||||
def OpGrp3RTS : OpGrp3<0x60>;
|
||||
def OpGrp3SEC : OpGrp3<0x38>;
|
||||
def OpGrp3SED : OpGrp3<0xF8>;
|
||||
def OpGrp3SEI : OpGrp3<0x78>;
|
||||
def OpGrp3SEP : OpGrp3<0xE2>;
|
||||
def OpGrp3STP : OpGrp3<0xDB>;
|
||||
def OpGrp3STZabs : OpGrp3<0x9C>;
|
||||
def OpGrp3STZdp : OpGrp3<0x64>;
|
||||
def OpGrp3STZabsi : OpGrp3<0x9E>;
|
||||
def OpGrp3STZdpi : OpGrp3<0x74>;
|
||||
def OpGrp3TAX : OpGrp3<0xAA>;
|
||||
def OpGrp3TAY : OpGrp3<0xA8>;
|
||||
def OpGrp3TCD : OpGrp3<0x5B>;
|
||||
def OpGrp3TCS : OpGrp3<0x1B>;
|
||||
def OpGrp3TDC : OpGrp3<0x7B>;
|
||||
def OpGrp3TRBabs : OpGrp3<0x1C>;
|
||||
def OpGrp3TRBdp : OpGrp3<0x14>;
|
||||
def OpGrp3TSBabs : OpGrp3<0x0C>;
|
||||
def OpGrp3TSBdp : OpGrp3<0x04>;
|
||||
def OpGrp3TSC : OpGrp3<0x3B>;
|
||||
def OpGrp3TSX : OpGrp3<0xBA>;
|
||||
def OpGrp3TXA : OpGrp3<0x8A>;
|
||||
def OpGrp3TXS : OpGrp3<0x9A>;
|
||||
def OpGrp3TXY : OpGrp3<0x9B>;
|
||||
def OpGrp3TYA : OpGrp3<0x98>;
|
||||
def OpGrp3TYX : OpGrp3<0xB8>;
|
||||
def OpGrp3WAI : OpGrp3<0xCB>;
|
||||
def OpGrp3WDM : OpGrp3<0xCB>;
|
||||
def OpGrp3XBA : OpGrp3<0xEB>;
|
||||
def OpGrp3XCE : OpGrp3<0xFB>;
|
||||
|
||||
|
||||
class Group3<OpGrp3 opVal, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: InstWDC<outs, ins, asmstr, pattern> {
|
||||
OpGrp3 op = opVal;
|
||||
|
||||
let Inst = op.Value;
|
||||
}
|
1351
lib/Target/WDC65816/WDC65816InstrInfo.td
Normal file
1351
lib/Target/WDC65816/WDC65816InstrInfo.td
Normal file
File diff suppressed because it is too large
Load Diff
@ -31,10 +31,10 @@ WDC65816TargetMachine::WDC65816TargetMachine(const Target &T, StringRef TT,
|
||||
Reloc::Model RM, CodeModel::Model CM,
|
||||
CodeGenOpt::Level OL)
|
||||
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
|
||||
DL(Subtarget.getDataLayout()),
|
||||
InstrInfo(Subtarget),
|
||||
DL("e-p:32:8:8-i16:8:8-f32:8:8-f68:8:8-n16"),
|
||||
InstrInfo(),
|
||||
TLInfo(*this), TSInfo(*this),
|
||||
FrameLowering(Subtarget) {
|
||||
FrameLowering() {
|
||||
initAsmInfo();
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user