//===- WDCInstrInfo.td - Target Description for WDC 65816 Target ------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // // This file describes the WDC 65816 instructions in TableGen format. // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Instruction format superclass //===----------------------------------------------------------------------===// include "WDC65816InstrFormats.td" //===----------------------------------------------------------------------===// // Feature predicates. //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Instruction Pattern Stuff //===----------------------------------------------------------------------===// // Adressing modes. //def ADDRabs : ComplexPattern; //def ADDRabsl : ComplexPattern; //def ADDRdp : ComplexPattern; // Address operands def ADDRabs : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops ptr_rc, ptr_rc); } def ADDRabsl : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops ptr_rc, ptr_rc); } def ADDRdp : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops ptr_rc, ptr_rc); } //===----------------------------------------------------------------------===// // WDC 65816 Flag Conditions //===----------------------------------------------------------------------===// // Note that these values must be kept in sync with the CCOp::CondCode enum // values. //===----------------------------------------------------------------------===// // Instruction Class Templates //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// // Group #1 Instructions // JSR TODO - Need to set all of the DAG patterns // JSR TODO - Addresses are 32-bit to llvm but can we toss the upper byte for long addressing modes which are 24-bit // JSR TODO - Need to specify flag behaviour, especially carry for ADC, SBC, CMP def ADCimm : Group1$src2", [(set AccRegs:$dst, (add AccRegs:$src1, i16imm:$src2))]>; def ADCabs : Group1; def ADCabsl : Group1$src2", [(set AccRegs:$dst, (add AccRegs:$src1, (load ADDRabsl:$src2)))]>; def ADCdp : Group1; def ADCdpindir : Group1; def ADCdpindirl : Group1; def ADCabsix : Group1; def ADCabsiy : Group1; def ADCabsixl : Group1$src2,$src3", []>; def ADCdpix : Group1; def ADCdpiindirx : Group1; def ADCdpindiriy : Group1; def ADCdpindirliy : Group1; def ADCsr : Group1; def ADCsrindir : Group1; def ANDimm : Group1$src2", [(set AccRegs:$dst, (and AccRegs:$src1, i16imm:$src2))]>; def ANDabs : Group1; def ANDabsl : Group1$src2", [(set AccRegs:$dst, (and AccRegs:$src1, (load ADDRabsl:$src2)))]>; def ANDdp : Group1; def ANDdpindir : Group1; def ANDdpindirl : Group1; def ANDabsix : Group1; def ANDabsiy : Group1; def ANDabsixl : Group1$src2,$src3", []>; def ANDdpix : Group1; def ANDdpiindirx : Group1; def ANDdpindiriy : Group1; def ANDdpindirliy : Group1; def ANDsr : Group1; def ANDsrindir : Group1; def CMPimm : Group1$src2", []>; def CMPabs : Group1; def CMPabsl : Group1$src2", []>; def CMPdp : Group1; def CMPdpindir : Group1; def CMPdpindirl : Group1; def CMPabsix : Group1; def CMPabsiy : Group1; def CMPabsixl : Group1$src2,$src3", []>; def CMPdpix : Group1; def CMPdpiindirx : Group1; def CMPdpindiriy : Group1; def CMPdpindirliy : Group1; def CMPsr : Group1; def CMPsrindir : Group1; def EORimm : Group1$src2", [(set AccRegs:$dst, (xor AccRegs:$src1, i16imm:$src2))]>; def EORabs : Group1; def EORabsl : Group1$src2", [(set AccRegs:$dst, (xor AccRegs:$src1, (load ADDRabsl:$src2)))]>; def EORdp : Group1; def EORdpindir : Group1; def EORdpindirl : Group1; def EORabsix : Group1; def EORabsiy : Group1; def EORabsixl : Group1$src2,$src3", []>; def EORdpix : Group1; def EORdpiindirx : Group1; def EORdpindiriy : Group1; def EORdpindirliy : Group1; def EORsr : Group1; def EORsrindir : Group1; def LDAimm : Group1$src1", [(set AccRegs:$dst, i16imm:$src)]>; def LDAabs : Group1; def LDAabsl : Group1$src2", [(set AccRegs:$dst, (load ADDRabsl:$src2))]>; def LDAdp : Group1; def LDAdpindir : Group1; def LDAdpindirl : Group1; def LDAabsix : Group1; def LDAabsiy : Group1; def LDAabsixl : Group1$src2,$src3", []>; def LDAdpix : Group1; def LDAdpiindirx : Group1; def LDAdpindiriy : Group1; def LDAdpindirliy : Group1; def LDAsr : Group1; def LDAsrindir : Group1; def ORAimm : Group1$src2", [(set AccRegs:$dst, (or AccRegs:$src1, i16imm:$src2))]>; def ORAabs : Group1; def ORAabsl : Group1$src2", [(set AccRegs:$dst, (or AccRegs:$src1, (load ADDRabsl:$src2)))]>; def ORAdp : Group1; def ORAdpindir : Group1; def ORAdpindirl : Group1; def ORAabsix : Group1; def ORAabsiy : Group1; def ORAabsixl : Group1$src2,$src3", []>; def ORAdpix : Group1; def ORAdpiindirx : Group1; def ORAdpindiriy : Group1; def ORAdpindirliy : Group1; def ORAsr : Group1; def ORAsrindir : Group1; def SBCimm : Group1$src2", [(set AccRegs:$dst, (sub AccRegs:$src1, i16imm:$src2))]>; def SBCabs : Group1; def SBCabsl : Group1$src2", [(set AccRegs:$dst, (sub AccRegs:$src1, (load ADDRabsl:$src2)))]>; def SBCdp : Group1; def SBCdpindir : Group1; def SBCdpindirl : Group1; def SBCabsix : Group1; def SBCabsiy : Group1; def SBCabsixl : Group1$src2,$src3", []>; def SBCdpix : Group1; def SBCdpiindirx : Group1; def SBCdpindiriy : Group1; def SBCdpindirliy : Group1; def SBCsr : Group1; def SBCsrindir : Group1; def STAabs : Group1; def STAabsl : Group1$dst", [(store AccRegs:$src, ADDRabsl:$dst)]>; def STAdp : Group1; def STAdpindir : Group1; def STAdpindirl : Group1; def STAabsix : Group1; def STAabsiy : Group1; def STAabsixl : Group1$src2,$src3", []>; def STAdpix : Group1; def STAdpiindirx : Group1; def STAdpindiriy : Group1; def STAdpindirliy : Group1; def STAsr : Group1; def STAsrindir : Group1; // Group #2 Instructions def ASLacc : Group2; def ASLabs : Group2; def ASLdp : Group2; def ASLabsix : Group2; def ASLdpix : Group2; def DECacc : Group2; def DECabs : Group2; def DECdp : Group2; def DECabsix : Group2; def DECdpix : Group2; def INCacc : Group2; def INCabs : Group2; def INCdp : Group2; def INCabsix : Group2; def INCdpix : Group2; def LDXimm : Group2; def LDXabs : Group2; def LDXdp : Group2; def LDXabsiy : Group2; def LDXdpiy : Group2; def LDYimm : Group2_Y; def LDYabs : Group2_Y; def LDYdp : Group2_Y; def LDYabsix : Group2_Y; def LDYdpix : Group2_Y; def LSRacc : Group2; def LSRabs : Group2; def LSRdp : Group2; def LSRabsix : Group2; def LSRdpix : Group2; def ROLacc : Group2; def ROLabs : Group2; def ROLdp : Group2; def ROLabsix : Group2; def ROLdpix : Group2; def RORacc : Group2; def RORabs : Group2; def RORdp : Group2; def RORabsix : Group2; def RORdpix : Group2; def STXabs : Group2; def STXdp : Group2; def STXdpiy : Group2; def STYabs : Group2_Y; def STYdp : Group2_Y; def STYdpix : Group2_Y; // Group #3 Instructions def BCC : Group3; def BCS : Group3; def BEQ : Group3; def BITimm : Group3$src2", []>; def BITabs : Group3; def BITdp : Group3; def BITabsix : Group3; def BITdpix : Group3; def BMI : Group3; def BNE : Group3; def BPL : Group3; def BRA : Group3; def BRK : Group3; def BRL : Group3; def BVC : Group3; def BVS : Group3; def CLC : Group3; def CLD : Group3; def CLI : Group3; def CLV : Group3; def COP : Group3; def CPXimm : Group3; def CPXabs : Group3; def CPXdp : Group3; def CPYimm : Group3; def CPYabs : Group3; def CPYdp : Group3; def DEX : Group3; def DEY : Group3; def INX : Group3; def INY : Group3; def JMPabs : Group3; def JMPindir : Group3; def JMPindiri : Group3; def JMLabs : Group3$src", []>; def JMLindirl : Group3$src]", []>; def JSL : Group3$src", []>; def JSRabs : Group3; def JSRindiri : Group3; def MVN : Group3; def MVP : Group3; def NOP : Group3; def PEA : Group3; def PEI : Group3; def PER : Group3; def PHA : Group3; def PHB : Group3; def PHD : Group3; def PHK : Group3; def PHP : Group3; def PHX : Group3; def PHY : Group3; def PLA : Group3; def PLB : Group3; def PLD : Group3; def PLP : Group3; def PLX : Group3; def PLY : Group3; def REP : Group3; def RTI : Group3; def RTL : Group3; def RTS : Group3; def SEC : Group3; def SED : Group3; def SEI : Group3; def SEP : Group3; def STP : Group3; def STZabs : Group3; def STZdp : Group3; def STZabsi : Group3; def STZdpi : Group3; def TAX : Group3; def TAY : Group3; def TCD : Group3; def TCS : Group3; def TDC : Group3; def TRBabs : Group3; def TRBdp : Group3; def TSBabs : Group3; def TSBdp : Group3; def TSC : Group3; def TSX : Group3; def TXA : Group3; def TXS : Group3; def TXY : Group3; def TYA : Group3; def TYX : Group3; def WAI : Group3; def WDM : Group3; def XBA : Group3; def XCE : Group3; //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===//