mirror of
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601 lines
21 KiB
C++
601 lines
21 KiB
C++
//===-- AArch64BranchFixupPass.cpp - AArch64 branch fixup -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that fixes AArch64 branches which have ended up out
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// of range for their immediate operands.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "aarch64-branch-fixup"
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumSplit, "Number of uncond branches inserted");
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STATISTIC(NumCBrFixed, "Number of cond branches fixed");
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/// Return the worst case padding that could result from unknown offset bits.
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/// This does not include alignment padding caused by known offset bits.
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///
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/// @param LogAlign log2(alignment)
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/// @param KnownBits Number of known low offset bits.
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static inline unsigned UnknownPadding(unsigned LogAlign, unsigned KnownBits) {
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if (KnownBits < LogAlign)
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return (1u << LogAlign) - (1u << KnownBits);
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return 0;
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}
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namespace {
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/// Due to limited PC-relative displacements, conditional branches to distant
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/// blocks may need converting into an unconditional equivalent. For example:
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/// tbz w1, #0, far_away
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/// becomes
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/// tbnz w1, #0, skip
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/// b far_away
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/// skip:
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class AArch64BranchFixup : public MachineFunctionPass {
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/// Information about the offset and size of a single basic block.
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struct BasicBlockInfo {
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/// Distance from the beginning of the function to the beginning of this
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/// basic block.
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///
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/// Offsets are computed assuming worst case padding before an aligned
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/// block. This means that subtracting basic block offsets always gives a
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/// conservative estimate of the real distance which may be smaller.
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///
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/// Because worst case padding is used, the computed offset of an aligned
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/// block may not actually be aligned.
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unsigned Offset;
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/// Size of the basic block in bytes. If the block contains inline
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/// assembly, this is a worst case estimate.
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///
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/// The size does not include any alignment padding whether from the
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/// beginning of the block, or from an aligned jump table at the end.
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unsigned Size;
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/// The number of low bits in Offset that are known to be exact. The
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/// remaining bits of Offset are an upper bound.
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uint8_t KnownBits;
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/// When non-zero, the block contains instructions (inline asm) of unknown
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/// size. The real size may be smaller than Size bytes by a multiple of 1
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/// << Unalign.
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uint8_t Unalign;
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BasicBlockInfo() : Offset(0), Size(0), KnownBits(0), Unalign(0) {}
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/// Compute the number of known offset bits internally to this block.
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/// This number should be used to predict worst case padding when
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/// splitting the block.
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unsigned internalKnownBits() const {
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unsigned Bits = Unalign ? Unalign : KnownBits;
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// If the block size isn't a multiple of the known bits, assume the
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// worst case padding.
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if (Size & ((1u << Bits) - 1))
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Bits = countTrailingZeros(Size);
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return Bits;
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}
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/// Compute the offset immediately following this block. If LogAlign is
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/// specified, return the offset the successor block will get if it has
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/// this alignment.
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unsigned postOffset(unsigned LogAlign = 0) const {
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unsigned PO = Offset + Size;
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if (!LogAlign)
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return PO;
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// Add alignment padding from the terminator.
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return PO + UnknownPadding(LogAlign, internalKnownBits());
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}
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/// Compute the number of known low bits of postOffset. If this block
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/// contains inline asm, the number of known bits drops to the
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/// instruction alignment. An aligned terminator may increase the number
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/// of know bits.
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/// If LogAlign is given, also consider the alignment of the next block.
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unsigned postKnownBits(unsigned LogAlign = 0) const {
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return std::max(LogAlign, internalKnownBits());
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}
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};
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std::vector<BasicBlockInfo> BBInfo;
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/// One per immediate branch, keeping the machine instruction pointer,
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/// conditional or unconditional, the max displacement, and (if IsCond is
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/// true) the corresponding inverted branch opcode.
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struct ImmBranch {
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MachineInstr *MI;
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unsigned OffsetBits : 31;
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bool IsCond : 1;
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ImmBranch(MachineInstr *mi, unsigned offsetbits, bool cond)
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: MI(mi), OffsetBits(offsetbits), IsCond(cond) {}
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};
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/// Keep track of all the immediate branch instructions.
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///
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std::vector<ImmBranch> ImmBranches;
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MachineFunction *MF;
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const AArch64InstrInfo *TII;
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public:
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static char ID;
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AArch64BranchFixup() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "AArch64 branch fixup pass";
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}
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private:
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void initializeFunctionInfo();
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MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
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void adjustBBOffsetsAfter(MachineBasicBlock *BB);
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bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned OffsetBits);
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bool fixupImmediateBr(ImmBranch &Br);
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bool fixupConditionalBr(ImmBranch &Br);
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void computeBlockSize(MachineBasicBlock *MBB);
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unsigned getOffsetOf(MachineInstr *MI) const;
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void dumpBBs();
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void verify();
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};
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char AArch64BranchFixup::ID = 0;
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}
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/// check BBOffsets
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void AArch64BranchFixup::verify() {
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#ifndef NDEBUG
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for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock *MBB = MBBI;
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unsigned MBBId = MBB->getNumber();
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assert(!MBBId || BBInfo[MBBId - 1].postOffset() <= BBInfo[MBBId].Offset);
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}
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#endif
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}
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/// print block size and offset information - debugging
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void AArch64BranchFixup::dumpBBs() {
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DEBUG({
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for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
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const BasicBlockInfo &BBI = BBInfo[J];
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dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
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<< " kb=" << unsigned(BBI.KnownBits)
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<< " ua=" << unsigned(BBI.Unalign)
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<< format(" size=%#x\n", BBInfo[J].Size);
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}
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});
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}
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/// Returns an instance of the branch fixup pass.
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FunctionPass *llvm::createAArch64BranchFixupPass() {
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return new AArch64BranchFixup();
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}
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bool AArch64BranchFixup::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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DEBUG(dbgs() << "***** AArch64BranchFixup ******");
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TII = (const AArch64InstrInfo*)MF->getTarget().getInstrInfo();
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// This pass invalidates liveness information when it splits basic blocks.
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MF->getRegInfo().invalidateLiveness();
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// Renumber all of the machine basic blocks in the function, guaranteeing that
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// the numbers agree with the position of the block in the function.
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MF->RenumberBlocks();
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// Do the initial scan of the function, building up information about the
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// sizes of each block and location of each immediate branch.
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initializeFunctionInfo();
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// Iteratively fix up branches until there is no change.
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unsigned NoBRIters = 0;
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bool MadeChange = false;
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while (true) {
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DEBUG(dbgs() << "Beginning iteration #" << NoBRIters << '\n');
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bool BRChange = false;
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for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
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BRChange |= fixupImmediateBr(ImmBranches[i]);
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if (BRChange && ++NoBRIters > 30)
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report_fatal_error("Branch Fix Up pass failed to converge!");
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DEBUG(dumpBBs());
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if (!BRChange)
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break;
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MadeChange = true;
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}
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// After a while, this might be made debug-only, but it is not expensive.
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verify();
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DEBUG(dbgs() << '\n'; dumpBBs());
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BBInfo.clear();
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ImmBranches.clear();
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return MadeChange;
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}
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/// Return true if the specified basic block can fallthrough into the block
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/// immediately after it.
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static bool BBHasFallthrough(MachineBasicBlock *MBB) {
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// Get the next machine basic block in the function.
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MachineFunction::iterator MBBI = MBB;
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// Can't fall off end of function.
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if (llvm::next(MBBI) == MBB->getParent()->end())
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return false;
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MachineBasicBlock *NextBB = llvm::next(MBBI);
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for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
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E = MBB->succ_end(); I != E; ++I)
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if (*I == NextBB)
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return true;
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return false;
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}
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/// Do the initial scan of the function, building up information about the sizes
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/// of each block, and each immediate branch.
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void AArch64BranchFixup::initializeFunctionInfo() {
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BBInfo.clear();
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BBInfo.resize(MF->getNumBlockIDs());
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// First thing, compute the size of all basic blocks, and see if the function
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// has any inline assembly in it. If so, we have to be conservative about
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// alignment assumptions, as we don't know for sure the size of any
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// instructions in the inline assembly.
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for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
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computeBlockSize(I);
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// The known bits of the entry block offset are determined by the function
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// alignment.
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BBInfo.front().KnownBits = MF->getAlignment();
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// Compute block offsets and known bits.
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adjustBBOffsetsAfter(MF->begin());
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// Now go back through the instructions and build up our data structures.
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for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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if (I->isDebugValue())
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continue;
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int Opc = I->getOpcode();
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if (I->isBranch()) {
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bool IsCond = false;
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// The offsets encoded in instructions here scale by the instruction
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// size (4 bytes), effectively increasing their range by 2 bits.
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unsigned Bits = 0;
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switch (Opc) {
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default:
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continue; // Ignore other JT branches
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case AArch64::TBZxii:
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case AArch64::TBZwii:
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case AArch64::TBNZxii:
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case AArch64::TBNZwii:
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IsCond = true;
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Bits = 14 + 2;
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break;
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case AArch64::Bcc:
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case AArch64::CBZx:
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case AArch64::CBZw:
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case AArch64::CBNZx:
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case AArch64::CBNZw:
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IsCond = true;
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Bits = 19 + 2;
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break;
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case AArch64::Bimm:
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Bits = 26 + 2;
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break;
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}
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// Record this immediate branch.
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ImmBranches.push_back(ImmBranch(I, Bits, IsCond));
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}
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}
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}
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}
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/// Compute the size and some alignment information for MBB. This function
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/// updates BBInfo directly.
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void AArch64BranchFixup::computeBlockSize(MachineBasicBlock *MBB) {
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BasicBlockInfo &BBI = BBInfo[MBB->getNumber()];
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BBI.Size = 0;
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BBI.Unalign = 0;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
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++I) {
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BBI.Size += TII->getInstSizeInBytes(*I);
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// For inline asm, GetInstSizeInBytes returns a conservative estimate.
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// The actual size may be smaller, but still a multiple of the instr size.
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if (I->isInlineAsm())
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BBI.Unalign = 2;
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}
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}
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/// Return the current offset of the specified machine instruction from the
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/// start of the function. This offset changes as stuff is moved around inside
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/// the function.
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unsigned AArch64BranchFixup::getOffsetOf(MachineInstr *MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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// The offset is composed of two things: the sum of the sizes of all MBB's
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// before this instruction's block, and the offset from the start of the block
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// it is in.
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unsigned Offset = BBInfo[MBB->getNumber()].Offset;
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// Sum instructions before MI in MBB.
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for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
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assert(I != MBB->end() && "Didn't find MI in its own basic block?");
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Offset += TII->getInstSizeInBytes(*I);
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}
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return Offset;
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}
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/// Split the basic block containing MI into two blocks, which are joined by
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/// an unconditional branch. Update data structures and renumber blocks to
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/// account for this change and returns the newly created block.
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MachineBasicBlock *
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AArch64BranchFixup::splitBlockBeforeInstr(MachineInstr *MI) {
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MachineBasicBlock *OrigBB = MI->getParent();
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// Create a new MBB for the code after the OrigBB.
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MachineBasicBlock *NewBB =
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MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
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MachineFunction::iterator MBBI = OrigBB; ++MBBI;
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MF->insert(MBBI, NewBB);
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// Splice the instructions starting with MI over to NewBB.
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NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
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// Add an unconditional branch from OrigBB to NewBB.
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// Note the new unconditional branch is not being recorded.
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// There doesn't seem to be meaningful DebugInfo available; this doesn't
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// correspond to anything in the source.
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BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
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++NumSplit;
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// Update the CFG. All succs of OrigBB are now succs of NewBB.
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NewBB->transferSuccessors(OrigBB);
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// OrigBB branches to NewBB.
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OrigBB->addSuccessor(NewBB);
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// Update internal data structures to account for the newly inserted MBB.
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MF->RenumberBlocks(NewBB);
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// Insert an entry into BBInfo to align it properly with the (newly
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// renumbered) block numbers.
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BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
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// Figure out how large the OrigBB is. As the first half of the original
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// block, it cannot contain a tablejump. The size includes
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// the new jump we added. (It should be possible to do this without
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// recounting everything, but it's very confusing, and this is rarely
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// executed.)
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computeBlockSize(OrigBB);
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// Figure out how large the NewMBB is. As the second half of the original
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// block, it may contain a tablejump.
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computeBlockSize(NewBB);
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// All BBOffsets following these blocks must be modified.
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adjustBBOffsetsAfter(OrigBB);
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return NewBB;
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}
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void AArch64BranchFixup::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
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unsigned BBNum = BB->getNumber();
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for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
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// Get the offset and known bits at the end of the layout predecessor.
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// Include the alignment of the current block.
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unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
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unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
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unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
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// This is where block i begins. Stop if the offset is already correct,
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// and we have updated 2 blocks. This is the maximum number of blocks
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// changed before calling this function.
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if (i > BBNum + 2 &&
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BBInfo[i].Offset == Offset &&
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BBInfo[i].KnownBits == KnownBits)
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break;
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BBInfo[i].Offset = Offset;
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BBInfo[i].KnownBits = KnownBits;
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}
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}
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/// Returns true if the distance between specific MI and specific BB can fit in
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/// MI's displacement field.
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bool AArch64BranchFixup::isBBInRange(MachineInstr *MI,
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MachineBasicBlock *DestBB,
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unsigned OffsetBits) {
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int64_t BrOffset = getOffsetOf(MI);
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int64_t DestOffset = BBInfo[DestBB->getNumber()].Offset;
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DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
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<< " from BB#" << MI->getParent()->getNumber()
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<< " bits available=" << OffsetBits
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<< " from " << getOffsetOf(MI) << " to " << DestOffset
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<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
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return isIntN(OffsetBits, DestOffset - BrOffset);
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}
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/// Fix up an immediate branch whose destination is too far away to fit in its
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/// displacement field.
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bool AArch64BranchFixup::fixupImmediateBr(ImmBranch &Br) {
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MachineInstr *MI = Br.MI;
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MachineBasicBlock *DestBB = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (MI->getOperand(i).isMBB()) {
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DestBB = MI->getOperand(i).getMBB();
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break;
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}
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}
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assert(DestBB && "Branch with no destination BB?");
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// Check to see if the DestBB is already in-range.
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if (isBBInRange(MI, DestBB, Br.OffsetBits))
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return false;
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assert(Br.IsCond && "Only conditional branches should need fixup");
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return fixupConditionalBr(Br);
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}
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/// Fix up a conditional branch whose destination is too far away to fit in its
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/// displacement field. It is converted to an inverse conditional branch + an
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/// unconditional branch to the destination.
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bool
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AArch64BranchFixup::fixupConditionalBr(ImmBranch &Br) {
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MachineInstr *MI = Br.MI;
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MachineBasicBlock *MBB = MI->getParent();
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unsigned CondBrMBBOperand = 0;
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// The general idea is to add an unconditional branch to the destination and
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// invert the conditional branch to jump over it. Complications occur around
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// fallthrough and unreachable ends to the block.
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// b.lt L1
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// =>
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// b.ge L2
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// b L1
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// L2:
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// First we invert the conditional branch, by creating a replacement if
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// necessary. This if statement contains all the special handling of different
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// branch types.
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if (MI->getOpcode() == AArch64::Bcc) {
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// The basic block is operand number 1 for Bcc
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CondBrMBBOperand = 1;
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A64CC::CondCodes CC = (A64CC::CondCodes)MI->getOperand(0).getImm();
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CC = A64InvertCondCode(CC);
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MI->getOperand(0).setImm(CC);
|
|
} else {
|
|
MachineInstrBuilder InvertedMI;
|
|
int InvertedOpcode;
|
|
switch (MI->getOpcode()) {
|
|
default: llvm_unreachable("Unknown branch type");
|
|
case AArch64::TBZxii: InvertedOpcode = AArch64::TBNZxii; break;
|
|
case AArch64::TBZwii: InvertedOpcode = AArch64::TBNZwii; break;
|
|
case AArch64::TBNZxii: InvertedOpcode = AArch64::TBZxii; break;
|
|
case AArch64::TBNZwii: InvertedOpcode = AArch64::TBZwii; break;
|
|
case AArch64::CBZx: InvertedOpcode = AArch64::CBNZx; break;
|
|
case AArch64::CBZw: InvertedOpcode = AArch64::CBNZw; break;
|
|
case AArch64::CBNZx: InvertedOpcode = AArch64::CBZx; break;
|
|
case AArch64::CBNZw: InvertedOpcode = AArch64::CBZw; break;
|
|
}
|
|
|
|
InvertedMI = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(InvertedOpcode));
|
|
for (unsigned i = 0, e= MI->getNumOperands(); i != e; ++i) {
|
|
InvertedMI.addOperand(MI->getOperand(i));
|
|
if (MI->getOperand(i).isMBB())
|
|
CondBrMBBOperand = i;
|
|
}
|
|
|
|
MI->eraseFromParent();
|
|
MI = Br.MI = InvertedMI;
|
|
}
|
|
|
|
// If the branch is at the end of its MBB and that has a fall-through block,
|
|
// direct the updated conditional branch to the fall-through
|
|
// block. Otherwise, split the MBB before the next instruction.
|
|
MachineInstr *BMI = &MBB->back();
|
|
bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
|
|
|
|
++NumCBrFixed;
|
|
if (BMI != MI) {
|
|
if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
|
|
BMI->getOpcode() == AArch64::Bimm) {
|
|
// Last MI in the BB is an unconditional branch. We can swap destinations:
|
|
// b.eq L1 (temporarily b.ne L1 after first change)
|
|
// b L2
|
|
// =>
|
|
// b.ne L2
|
|
// b L1
|
|
MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
|
|
if (isBBInRange(MI, NewDest, Br.OffsetBits)) {
|
|
DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
|
|
<< *BMI);
|
|
MachineBasicBlock *DestBB = MI->getOperand(CondBrMBBOperand).getMBB();
|
|
BMI->getOperand(0).setMBB(DestBB);
|
|
MI->getOperand(CondBrMBBOperand).setMBB(NewDest);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (NeedSplit) {
|
|
MachineBasicBlock::iterator MBBI = MI; ++MBBI;
|
|
splitBlockBeforeInstr(MBBI);
|
|
// No need for the branch to the next block. We're adding an unconditional
|
|
// branch to the destination.
|
|
int delta = TII->getInstSizeInBytes(MBB->back());
|
|
BBInfo[MBB->getNumber()].Size -= delta;
|
|
MBB->back().eraseFromParent();
|
|
// BBInfo[SplitBB].Offset is wrong temporarily, fixed below
|
|
}
|
|
|
|
// After splitting and removing the unconditional branch from the original BB,
|
|
// the structure is now:
|
|
// oldbb:
|
|
// [things]
|
|
// b.invertedCC L1
|
|
// splitbb/fallthroughbb:
|
|
// [old b L2/real continuation]
|
|
//
|
|
// We now have to change the conditional branch to point to splitbb and add an
|
|
// unconditional branch after it to L1, giving the final structure:
|
|
// oldbb:
|
|
// [things]
|
|
// b.invertedCC splitbb
|
|
// b L1
|
|
// splitbb/fallthroughbb:
|
|
// [old b L2/real continuation]
|
|
MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
|
|
|
|
DEBUG(dbgs() << " Insert B to BB#"
|
|
<< MI->getOperand(CondBrMBBOperand).getMBB()->getNumber()
|
|
<< " also invert condition and change dest. to BB#"
|
|
<< NextBB->getNumber() << "\n");
|
|
|
|
// Insert a new unconditional branch and fixup the destination of the
|
|
// conditional one. Also update the ImmBranch as well as adding a new entry
|
|
// for the new branch.
|
|
BuildMI(MBB, DebugLoc(), TII->get(AArch64::Bimm))
|
|
.addMBB(MI->getOperand(CondBrMBBOperand).getMBB());
|
|
MI->getOperand(CondBrMBBOperand).setMBB(NextBB);
|
|
|
|
BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
|
|
|
|
// 26 bits written down in Bimm, specifying a multiple of 4.
|
|
unsigned OffsetBits = 26 + 2;
|
|
ImmBranches.push_back(ImmBranch(&MBB->back(), OffsetBits, false));
|
|
|
|
adjustBBOffsetsAfter(MBB);
|
|
return true;
|
|
}
|