mirror of
https://github.com/jeremysrand/llvm-65816.git
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291 lines
12 KiB
C++
291 lines
12 KiB
C++
//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for R600InstrInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef R600INSTRUCTIONINFO_H_
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#define R600INSTRUCTIONINFO_H_
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#include "AMDGPUInstrInfo.h"
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#include "R600Defines.h"
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#include "R600RegisterInfo.h"
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#include <map>
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namespace llvm {
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class AMDGPUTargetMachine;
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class DFAPacketizer;
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class ScheduleDAG;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class R600InstrInfo : public AMDGPUInstrInfo {
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private:
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const R600RegisterInfo RI;
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const AMDGPUSubtarget &ST;
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int getBranchInstr(const MachineOperand &op) const;
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std::vector<std::pair<int, unsigned> >
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ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
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public:
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enum BankSwizzle {
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ALU_VEC_012_SCL_210 = 0,
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ALU_VEC_021_SCL_122,
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ALU_VEC_120_SCL_212,
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ALU_VEC_102_SCL_221,
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ALU_VEC_201,
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ALU_VEC_210
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};
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explicit R600InstrInfo(AMDGPUTargetMachine &tm);
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const R600RegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const;
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bool isTrig(const MachineInstr &MI) const;
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bool isPlaceHolderOpcode(unsigned opcode) const;
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bool isReductionOp(unsigned opcode) const;
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bool isCubeOp(unsigned opcode) const;
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/// \returns true if this \p Opcode represents an ALU instruction.
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bool isALUInstr(unsigned Opcode) const;
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bool hasInstrModifiers(unsigned Opcode) const;
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bool isLDSInstr(unsigned Opcode) const;
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bool isLDSNoRetInstr(unsigned Opcode) const;
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bool isLDSRetInstr(unsigned Opcode) const;
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/// \returns true if this \p Opcode represents an ALU instruction or an
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/// instruction that will be lowered in ExpandSpecialInstrs Pass.
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bool canBeConsideredALU(const MachineInstr *MI) const;
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bool isTransOnly(unsigned Opcode) const;
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bool isTransOnly(const MachineInstr *MI) const;
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bool isVectorOnly(unsigned Opcode) const;
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bool isVectorOnly(const MachineInstr *MI) const;
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bool isExport(unsigned Opcode) const;
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bool usesVertexCache(unsigned Opcode) const;
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bool usesVertexCache(const MachineInstr *MI) const;
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bool usesTextureCache(unsigned Opcode) const;
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bool usesTextureCache(const MachineInstr *MI) const;
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bool mustBeLastInClause(unsigned Opcode) const;
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bool usesAddressRegister(MachineInstr *MI) const;
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bool definesAddressRegister(MachineInstr *MI) const;
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bool readsLDSSrcReg(const MachineInstr *MI) const;
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/// \returns The operand index for the given source number. Legal values
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/// for SrcNum are 0, 1, and 2.
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int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
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/// \returns The operand Index for the Sel operand given an index to one
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/// of the instruction's src operands.
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int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
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/// \returns a pair for each src of an ALU instructions.
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/// The first member of a pair is the register id.
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/// If register is ALU_CONST, second member is SEL.
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/// If register is ALU_LITERAL, second member is IMM.
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/// Otherwise, second member value is undefined.
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SmallVector<std::pair<MachineOperand *, int64_t>, 3>
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getSrcs(MachineInstr *MI) const;
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unsigned isLegalUpTo(
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const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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const std::vector<R600InstrInfo::BankSwizzle> &Swz,
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const std::vector<std::pair<int, unsigned> > &TransSrcs,
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R600InstrInfo::BankSwizzle TransSwz) const;
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bool FindSwizzleForVectorSlot(
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const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
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std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
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const std::vector<std::pair<int, unsigned> > &TransSrcs,
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R600InstrInfo::BankSwizzle TransSwz) const;
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/// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
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/// returns true and the first (in lexical order) BankSwizzle affectation
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/// starting from the one already provided in the Instruction Group MIs that
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/// fits Read Port limitations in BS if available. Otherwise returns false
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/// and undefined content in BS.
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/// isLastAluTrans should be set if the last Alu of MIs will be executed on
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/// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
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/// apply to the last instruction.
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/// PV holds GPR to PV registers in the Instruction Group MIs.
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bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<BankSwizzle> &BS,
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bool isLastAluTrans) const;
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/// An instruction group can only access 2 channel pair (either [XY] or [ZW])
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/// from KCache bank on R700+. This function check if MI set in input meet
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/// this limitations
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bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
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/// Same but using const index set instead of MI set.
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bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
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/// \breif Vector instructions are instructions that must fill all
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/// instruction slots within an instruction group.
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bool isVector(const MachineInstr &MI) const;
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virtual unsigned getIEQOpcode() const;
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virtual bool isMov(unsigned Opcode) const;
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DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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bool isPredicated(const MachineInstr *MI) const;
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bool isPredicable(MachineInstr *MI) const;
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bool
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isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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const BranchProbability &Probability) const;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const ;
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bool
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isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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const BranchProbability &Probability) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const;
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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unsigned int getPredicationCost(const MachineInstr *) const;
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unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const;
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virtual int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const { return 1;}
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/// \brief Reserve the registers that may be accesed using indirect addressing.
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void reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF) const;
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virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const;
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virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
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virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg) const;
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virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg, unsigned Address,
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unsigned OffsetReg) const;
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unsigned getMaxAlusPerClause() const;
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///buildDefaultInstruction - This function returns a MachineInstr with
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/// all the instruction modifiers initialized to their default values.
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/// You can use this function to avoid manually specifying each instruction
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/// modifier operand when building a new instruction.
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///
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/// \returns a MachineInstr with all the instruction modifiers initialized
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/// to their default values.
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MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned Opcode,
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unsigned DstReg,
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unsigned Src0Reg,
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unsigned Src1Reg = 0) const;
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MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
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MachineInstr *MI,
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unsigned Slot,
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unsigned DstReg) const;
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MachineInstr *buildMovImm(MachineBasicBlock &BB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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uint64_t Imm) const;
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MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const;
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/// \brief Get the index of Op in the MachineInstr.
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///
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/// \returns -1 if the Instruction does not contain the specified \p Op.
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int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
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/// \brief Get the index of \p Op for the given Opcode.
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///
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/// \returns -1 if the Instruction does not contain the specified \p Op.
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int getOperandIdx(unsigned Opcode, unsigned Op) const;
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/// \brief Helper function for setting instruction flag values.
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void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
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/// \returns true if this instruction has an operand for storing target flags.
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bool hasFlagOperand(const MachineInstr &MI) const;
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///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
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void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
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///\brief Determine if the specified \p Flag is set on this \p Operand.
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bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
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/// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
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/// \param Flag The flag being set.
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///
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/// \returns the operand containing the flags for this instruction.
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MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
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unsigned Flag = 0) const;
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/// \brief Clear the specified flag on the instruction.
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void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
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};
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namespace AMDGPU {
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int getLDSNoRetOp(uint16_t Opcode);
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} //End namespace AMDGPU
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} // End llvm namespace
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#endif // R600INSTRINFO_H_
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