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https://github.com/jeremysrand/llvm-65816.git
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89 lines
3.0 KiB
C++
89 lines
3.0 KiB
C++
//===-- llvm/CodeGen/LiveRegUnits.h - Live register unit set ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a Set of live register units. This can be used for ad
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// hoc liveness tracking after register allocation. You can start with the
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// live-ins/live-outs at the beginning/end of a block and update the information
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// while walking the instructions inside the block.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
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#define LLVM_CODEGEN_LIVEREGUNITS_H
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#include "llvm/ADT/SparseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <cassert>
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namespace llvm {
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class MachineInstr;
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/// A set of live register units with functions to track liveness when walking
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/// backward/forward through a basic block.
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class LiveRegUnits {
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SparseSet<unsigned> LiveUnits;
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LiveRegUnits(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
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LiveRegUnits &operator=(const LiveRegUnits&) LLVM_DELETED_FUNCTION;
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public:
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/// \brief Constructs a new empty LiveRegUnits set.
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LiveRegUnits() {}
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void init(const TargetRegisterInfo *TRI) {
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LiveUnits.clear();
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LiveUnits.setUniverse(TRI->getNumRegs());
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}
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void clear() { LiveUnits.clear(); }
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bool empty() const { return LiveUnits.empty(); }
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/// \brief Adds a register to the set.
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void addReg(unsigned Reg, const MCRegisterInfo &MCRI) {
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for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
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LiveUnits.insert(*RUnits);
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}
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/// \brief Removes a register from the set.
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void removeReg(unsigned Reg, const MCRegisterInfo &MCRI) {
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for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits)
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LiveUnits.erase(*RUnits);
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}
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/// \brief Removes registers clobbered by the regmask operand @p Op.
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void removeRegsInMask(const MachineOperand &Op, const MCRegisterInfo &MCRI);
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/// \brief Returns true if register @p Reg (or one of its super register) is
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/// contained in the set.
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bool contains(unsigned Reg, const MCRegisterInfo &MCRI) const {
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for (MCRegUnitIterator RUnits(Reg, &MCRI); RUnits.isValid(); ++RUnits) {
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if (LiveUnits.count(*RUnits))
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return true;
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}
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return false;
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}
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/// \brief Simulates liveness when stepping backwards over an
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/// instruction(bundle): Remove Defs, add uses.
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void stepBackward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
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/// \brief Simulates liveness when stepping forward over an
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/// instruction(bundle): Remove killed-uses, add defs.
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void stepForward(const MachineInstr &MI, const MCRegisterInfo &MCRI);
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/// \brief Adds all registers in the live-in list of block @p BB.
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void addLiveIns(const MachineBasicBlock *MBB, const MCRegisterInfo &MCRI);
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};
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} // namespace llvm
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#endif
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