mirror of
https://github.com/jeremysrand/llvm-65816.git
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256 lines
9.4 KiB
C++
256 lines
9.4 KiB
C++
//===- WDC65816ISelDAGToDAG.cpp - A dag to dag inst selector for WDC65816 -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the WDC65816 target.
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//
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//===----------------------------------------------------------------------===//
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#include "WDC65816TargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// WDC65816DAGToDAGISel - WDC65816 specific code to select WDC65816 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class WDC65816DAGToDAGISel : public SelectionDAGISel {
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const WDC65816Subtarget &Subtarget;
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WDC65816TargetMachine &TM;
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public:
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explicit WDC65816DAGToDAGISel(WDC65816TargetMachine &tm)
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: SelectionDAGISel(tm), Subtarget(tm.getSubtarget<WDC65816Subtarget>()),
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TM(tm) {
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}
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SDNode *Select(SDNode *N);
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bool SelectAbs(SDValue N, SDValue &R1);
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bool SelectAbsLong(SDValue N, SDValue &R1);
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bool SelectDirectPage(SDValue N, SDValue &R1);
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#if 0 // WDC_TODO - we don't need these pattern selectors but we will need some
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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#endif
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virtual const char *getPassName() const {
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return "WDC65816 DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "WDC65816GenDAGISel.inc"
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private:
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SDNode* getGlobalBaseReg();
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};
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} // end anonymous namespace
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SDNode* WDC65816DAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
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WDC_LOG("WDC_TODO - This method is probably implemented wrong...");
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return CurDAG->getRegister(GlobalBaseReg,
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getTargetLowering()->getPointerTy()).getNode();
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}
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bool WDC65816DAGToDAGISel::SelectAbs(SDValue N, SDValue &R1) {
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WDC_LOG("WDC_TODO - Unimplemented method called");
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return false;
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}
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bool WDC65816DAGToDAGISel::SelectAbsLong(SDValue N, SDValue &R1) {
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WDC_LOG("WDC_TODO - Unimplemented method called");
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return false;
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}
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bool WDC65816DAGToDAGISel::SelectDirectPage(SDValue N, SDValue &R1) {
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WDC_LOG("WDC_TODO - Unimplemented method called");
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return false;
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}
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#if 0 // WDC_TODO - we don't need these exactly, we need out own
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bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
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getTargetLowering()->getPointerTy());
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (isInt<13>(CN->getSExtValue())) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
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getTargetLowering()->getPointerTy());
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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return true;
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}
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}
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(1);
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (isInt<13>(CN->getSExtValue()))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
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Addr.getOperand(1).getOpcode() == SPISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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return true;
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}
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R1 = Addr;
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R2 = CurDAG->getRegister(SP::G0, getTargetLowering()->getPointerTy());
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return true;
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}
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#endif
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SDNode *WDC65816DAGToDAGISel::Select(SDNode *N) {
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WDC_LOG("WDC_TODO - Unimplemented method called, opcode=" << N);
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SDLoc dl(N);
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return NULL; // Already selected.
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}
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switch (N->getOpcode()) {
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default: break;
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#if 0 // WDC_TODO - Do I need any of this
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case SPISD::GLOBAL_BASE_REG:
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return getGlobalBaseReg();
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case ISD::SDIV:
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case ISD::UDIV: {
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// sdivx / udivx handle 64-bit divides.
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if (N->getValueType(0) == MVT::i64)
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break;
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDValue DivLHS = N->getOperand(0);
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SDValue DivRHS = N->getOperand(1);
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// Set the Y register to the high-part.
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SDValue TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32)), 0);
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} else {
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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}
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TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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TopPart);
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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// FIXME: Handle mul by immediate.
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SDValue MulLHS = N->getOperand(0);
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SDValue MulRHS = N->getOperand(1);
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
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SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
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MulLHS, MulRHS);
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// The high part is in the Y register.
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
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}
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#endif
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}
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return SelectCode(N);
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}
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#if 0 // WDC_TODO - Not sure what this is about...
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool
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SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectADDRrr(Op, Op0, Op1))
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SelectADDRri(Op, Op0, Op1);
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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#endif
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/// createWDC65816ISelDag - This pass converts a legalized DAG into a
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/// WDC65816-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createWDC65816ISelDag(WDC65816TargetMachine &TM) {
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WDC_LOG("ISel DAG created");
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return new WDC65816DAGToDAGISel(TM);
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}
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