2019-07-15 12:21:50 +00:00
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[< back to index](../doc_index.md)
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2018-04-02 22:21:26 +00:00
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2018-01-04 00:15:04 +00:00
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# Undocumented opcodes
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2018-07-27 17:07:12 +00:00
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## 6502
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2018-01-04 00:15:04 +00:00
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Original 6502 processors accidentally supported a bunch of extra undocumented instructions.
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Millfork can emit them if so desired.
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2019-03-18 22:15:28 +00:00
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#### Mnemonics
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2018-01-04 00:15:04 +00:00
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Since various assemblers use different mnemonics for undocumented opcodes,
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Millfork supports multiple mnemonics per opcode. The default one is given first:
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* **AHX**, AXA, SHA
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* **ALR**
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* **ANC**
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* **ARR**
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* **DCP**, DCM
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* **ISC**, INS
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2020-01-17 23:09:06 +00:00
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* **KIL**
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2018-01-04 00:15:04 +00:00
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* **LAS**
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* **LAX**
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* **LXA**, OAL
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* **RLA**
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* **RRA**
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2018-03-03 00:21:57 +00:00
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* **SAX**\*
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2018-01-04 00:15:04 +00:00
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* **SHX**, XAS
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2018-03-03 00:21:57 +00:00
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* **SHY**, SAY\*
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2018-01-04 00:15:04 +00:00
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2018-03-03 00:21:57 +00:00
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* **SBX**, AXS\*\*
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2018-01-04 00:15:04 +00:00
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* **SRE**, LSE
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* **SLO**, ASO
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* **TAS**
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* **XAA**, ANE
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2018-03-03 00:21:57 +00:00
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\* HuC2680 has different instructions also called SAX and SAY,
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but Millfork can distinguish between them and the NMOS illegal instructions based on the addressing mode.
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\*\* AXS is also used for SAX in some assemblers. Millfork interprets AXS based on the addressing mode.
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2018-01-04 00:15:04 +00:00
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2019-03-18 22:15:28 +00:00
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#### Generation
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2018-01-04 00:15:04 +00:00
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In order for the compiler to emit one of those opcodes,
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an appropriate CPU architecture must be chosen (`nmos` or `ricoh`)
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and either it must appear in an assembly block or it may be a result of optimization.
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Optimization will never emit any of the following opcodes due to their instability and/or uselessness:
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AHX, LAS, LXA, SHX, SHY, TAS, XAA.
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2018-07-27 17:07:12 +00:00
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## Z80
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Original Z80 processors accidentally supported a bunch of extra undocumented instructions.
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2020-07-24 15:27:37 +00:00
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Millfork will emit some of them if used in an assembly block:
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* `SLL` – supported
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* instructions using the IXH, IXL, IYH, IYL registers – supported (can only be used in Zilog syntax)
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* instructions of the form `RLC IX(1),B` – not supported
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2019-05-31 15:03:35 +00:00
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2019-06-12 10:06:02 +00:00
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## 8085
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Since various assemblers use different mnemonics for undocumented opcodes,
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Millfork supports multiple mnemonics per opcode. The default one is given first:
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Intel syntax | Zilog syntax
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2019-08-05 12:07:33 +00:00
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----|----
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2019-06-12 10:06:02 +00:00
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**DSUB** | **DSUB**
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**ARHL**, RRHL | **SRA HL**
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**RLDE**, RDEL | **RL DE**
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**LDHI n** | **LD DE,(HL+n)**
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**LDSI n** | **LD DE,(SP+n)**
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**LHLX** | **LD HL,(DE)**
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**SHLX** | **LD (DE),HL**
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**JK n**, JX5 n | **JP K,n**; JP X5,n
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**JNK n**, JNX5 n | **JP NK,n**; JP NX5,n
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**RSTV**, OVRST8 | **RSTV**
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#### Generation
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If enabled, The compiler will only emit the following undocumented instructions from Millfork code:
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DSUB, LHLX, SHLX, LDSI, LDHI
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The optimizer does not track the K and V flags. Use `JK`, `JNK` and `RSTV` with care.
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2019-05-31 15:03:35 +00:00
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## 8086
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Undocumented instructions are not supported.
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