2018-09-28 21:45:26 +00:00
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#if not(ARCH_I80)
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#warn i80_math module should be used only on 8080-like targets
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#endif
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#pragma zilog_syntax
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#if CPUFEATURE_Z80 || CPUFEATURE_GAMEBOY
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2018-12-19 00:09:27 +00:00
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noinline asm byte __mul_u8u8u8() {
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2018-09-28 21:45:26 +00:00
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? LD E,A
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? LD A, 0
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? JR __mul_u8u8u8_start
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__mul_u8u8u8_add:
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? ADD A,E
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__mul_u8u8u8_loop:
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? SLA E
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__mul_u8u8u8_start:
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? SRL D
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? JR C, __mul_u8u8u8_add
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? JR NZ, __mul_u8u8u8_loop
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? RET
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}
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#else
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2018-12-19 00:09:27 +00:00
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noinline asm byte __mul_u8u8u8() {
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2018-09-28 21:45:26 +00:00
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? LD E,A
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? LD C, 0
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? JP __mul_u8u8u8_start
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__mul_u8u8u8_add:
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? LD A,C
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? ADD A,E
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? LD C,A
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__mul_u8u8u8_loop:
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? LD A,E
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? ADD A,A
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? LD E,A
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__mul_u8u8u8_start:
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? OR A
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? LD A,D
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? RRA
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? LD D,A
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? JP C, __mul_u8u8u8_add
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? OR A
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? JP NZ, __mul_u8u8u8_loop
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? LD A,C
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? RET
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}
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#endif
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2018-12-14 21:50:20 +00:00
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inline asm word __mul_u16u8u16() {
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? LD HL,0
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? LD B,8
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__mul_u16u8u16_loop:
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? ADD HL,HL
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? ADC A,A
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#if CPUFEATURE_Z80 || CPUFEATURE_GAMEBOY
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? JR NC,__mul_u16u8u16_skip
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#else
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? JP NC,__mul_u16u8u16_skip
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#endif
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? ADD HL,DE
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__mul_u16u8u16_skip:
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#if CPUFEATURE_Z80
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? DJNZ __mul_u16u8u16_loop
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#elseif CPUFEATURE_GAMEBOY
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? DEC B
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? JR NZ,__mul_u16u8u16_loop
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#else
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? DEC B
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? JP NZ,__mul_u16u8u16_loop
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#endif
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? RET
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}
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