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Fix the sieve benchmark

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This commit is contained in:
Karol Stasiak 2019-10-23 11:52:42 +02:00
parent 9beac45e99
commit 010647682a
5 changed files with 32 additions and 3 deletions
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4
CHANGELOG.md
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@ -22,6 +22,10 @@
* Fixed a bug with variable overlapping (#11). * Fixed a bug with variable overlapping (#11).
* 6502: Fixed a bug with flow analysis during optimizations.
* 6502: Fixed a bug with certain 16-bit additions.
* 8080: Fixed and optimized 16-bit comparisons. * 8080: Fixed and optimized 16-bit comparisons.
* 8080: Optimized some library functions. * 8080: Optimized some library functions.

10
src/main/scala/millfork/assembly/mos/opt/CpuStatus.scala
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@ -214,6 +214,8 @@ object CpuStatus {
v = AnyStatus, v = AnyStatus,
z = AnyStatus, z = AnyStatus,
n = AnyStatus, n = AnyStatus,
a0 = AnyStatus,
a7 = AnyStatus,
d = SingleStatus(false), d = SingleStatus(false),
m = SingleStatus(true), m = SingleStatus(true),
w = SingleStatus(true), w = SingleStatus(true),
@ -231,6 +233,8 @@ object CpuStatus {
v = AnyStatus, v = AnyStatus,
z = AnyStatus, z = AnyStatus,
n = AnyStatus, n = AnyStatus,
a0 = AnyStatus,
a7 = AnyStatus,
d = SingleStatus(false), d = SingleStatus(false),
m = SingleStatus(true), m = SingleStatus(true),
w = SingleStatus(true), w = SingleStatus(true),
@ -249,6 +253,8 @@ object CpuStatus {
v = AnyStatus, v = AnyStatus,
z = AnyStatus, z = AnyStatus,
n = AnyStatus, n = AnyStatus,
a0 = AnyStatus,
a7 = AnyStatus,
d = AnyStatus, d = AnyStatus,
m = AnyStatus, m = AnyStatus,
w = AnyStatus, w = AnyStatus,
@ -266,6 +272,8 @@ object CpuStatus {
v = AnyStatus, v = AnyStatus,
z = AnyStatus, z = AnyStatus,
n = AnyStatus, n = AnyStatus,
a0 = AnyStatus,
a7 = AnyStatus,
d = SingleStatus(false), d = SingleStatus(false),
m = AnyStatus, m = AnyStatus,
w = AnyStatus, w = AnyStatus,
@ -283,6 +291,8 @@ object CpuStatus {
v = AnyStatus, v = AnyStatus,
z = AnyStatus, z = AnyStatus,
n = AnyStatus, n = AnyStatus,
a0 = AnyStatus,
a7 = AnyStatus,
d = SingleStatus(false), d = SingleStatus(false),
m = AnyStatus, m = AnyStatus,
w = AnyStatus, w = AnyStatus,

4
src/main/scala/millfork/compiler/mos/PseudoregisterBuiltIns.scala
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@ -45,7 +45,7 @@ object PseudoregisterBuiltIns {
case List(AssemblyLine0(LDA, Immediate, l), AssemblyLine0(LDX, Immediate, h)) => case List(AssemblyLine0(LDA, Immediate, l), AssemblyLine0(LDX, Immediate, h)) =>
if (subtract) constant -= h.asl(8).+(l).quickSimplify if (subtract) constant -= h.asl(8).+(l).quickSimplify
else constant += h.asl(8).+(l).quickSimplify else constant += h.asl(8).+(l).quickSimplify
case List(l@AssemblyLine0(LDA, Absolute | ZeroPage | Immediate, _), h@AssemblyLine0(LDX, Absolute | ZeroPage | Immediate, _)) => case List(l@AssemblyLine0(LDA, Absolute | ZeroPage | Immediate | LongAbsolute, _), h@AssemblyLine0(LDX, Absolute | ZeroPage | Immediate | LongAbsolute, _)) =>
if (subtract) niceReads.+=(List(AssemblyLine.implied(SEC), l.copy(opcode = SBC)) -> List(h.copy(opcode = SBC))) if (subtract) niceReads.+=(List(AssemblyLine.implied(SEC), l.copy(opcode = SBC)) -> List(h.copy(opcode = SBC)))
else niceReads += (List(AssemblyLine.implied(CLC), l.copy(opcode = ADC)) -> List(h.copy(opcode = ADC))) else niceReads += (List(AssemblyLine.implied(CLC), l.copy(opcode = ADC)) -> List(h.copy(opcode = ADC)))
counter += 1 counter += 1
@ -68,7 +68,7 @@ object PseudoregisterBuiltIns {
if (constant.isQuiteNegative) { if (constant.isQuiteNegative) {
niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte)) niceReads += List(AssemblyLine.implied(CLC), AssemblyLine.immediate(ADC, constant.loByte)) -> List(AssemblyLine.immediate(ADC, constant.hiByte))
} else { } else {
val negC = Constant.Zero.-(constant).quickSimplify.quickSimplify val negC = Constant.WordZero.-(constant).quickSimplify.quickSimplify
niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte)) niceReads += List(AssemblyLine.implied(SEC), AssemblyLine.immediate(SBC, negC.loByte)) -> List(AssemblyLine.immediate(SBC, negC.hiByte))
} }
} }

2
src/main/scala/millfork/env/Constant.scala vendored
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@ -40,7 +40,7 @@ sealed trait Constant {
case _ => CompoundConstant(MathOperator.Shl, this, i) case _ => CompoundConstant(MathOperator.Shl, this, i)
} }
def asl(i: Int): Constant = CompoundConstant(MathOperator.Shl, this, NumericConstant(i, 1)) def asl(i: Int): Constant = CompoundConstant(MathOperator.Shl, this, NumericConstant(i, requiredSize + i/8))
def requiredSize: Int def requiredSize: Int

15
src/test/scala/millfork/test/WordMathSuite.scala
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@ -20,6 +20,21 @@ class WordMathSuite extends FunSuite with Matchers with AppendedClues {
""".stripMargin)(_.readWord(0xc000) should equal(1280)) """.stripMargin)(_.readWord(0xc000) should equal(1280))
} }
test("Addition that was buggy") {
EmuCrossPlatformBenchmarkRun(Cpu.Mos, Cpu.Z80, Cpu.Motorola6809)("""
| word output @$c000
| array X [$1000] align($100)
| void main () {
| output = f(1)
| }
| noinline word f(byte I) {
| word S
| S = X + nonet(I << 1)
| return S
| }
""".stripMargin)(_.readWord(0xc000) should equal(0x302))
}
test("Cast word addition") { test("Cast word addition") {
EmuCrossPlatformBenchmarkRun(Cpu.Sixteen, Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Intel8085, Cpu.Sharp, Cpu.Intel8086, Cpu.Motorola6809)(""" EmuCrossPlatformBenchmarkRun(Cpu.Sixteen, Cpu.Mos, Cpu.Z80, Cpu.Intel8080, Cpu.Intel8085, Cpu.Sharp, Cpu.Intel8086, Cpu.Motorola6809)("""
| byte output @$c000 | byte output @$c000