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Flow analyser should correctly analyse INC A and DEC A

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Karol Stasiak
2017-12-18 10:09:25 +01:00
parent 2779671300
commit 081e3bc55c
2 changed files with 8 additions and 0 deletions
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4
src/main/scala/millfork/assembly/opt/CoarseFlowAnalyzer.scala
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@@ -223,6 +223,10 @@ object CoarseFlowAnalyzer {
currentStatus = currentStatus.copy(n = currentStatus.y.n(_ + 1), z = currentStatus.y.z(_ + 1), y = currentStatus.y.map(_ + 1)) currentStatus = currentStatus.copy(n = currentStatus.y.n(_ + 1), z = currentStatus.y.z(_ + 1), y = currentStatus.y.map(_ + 1))
case AssemblyLine(DEY, Implied, _, _) => case AssemblyLine(DEY, Implied, _, _) =>
currentStatus = currentStatus.copy(n = currentStatus.y.n(_ - 1), z = currentStatus.y.z(_ - 1), y = currentStatus.y.map(_ - 1)) currentStatus = currentStatus.copy(n = currentStatus.y.n(_ - 1), z = currentStatus.y.z(_ - 1), y = currentStatus.y.map(_ - 1))
case AssemblyLine(INC, Implied, _, _) =>
currentStatus = currentStatus.copy(n = currentStatus.a.n(_ + 1), z = currentStatus.a.z(_ + 1), a = currentStatus.a.map(_ + 1))
case AssemblyLine(DEC, Implied, _, _) =>
currentStatus = currentStatus.copy(n = currentStatus.a.n(_ - 1), z = currentStatus.a.z(_ - 1), a = currentStatus.a.map(_ - 1))
case AssemblyLine(TAX, _, _, _) => case AssemblyLine(TAX, _, _, _) =>
currentStatus = currentStatus.copy(x = currentStatus.a, n = currentStatus.a.n(), z = currentStatus.a.z()) currentStatus = currentStatus.copy(x = currentStatus.a, n = currentStatus.a.n(), z = currentStatus.a.z())
case AssemblyLine(TXA, _, _, _) => case AssemblyLine(TXA, _, _, _) =>

4
src/main/scala/millfork/assembly/opt/QuantumFlowAnalyzer.scala
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@@ -308,6 +308,10 @@ object QuantumFlowAnalyzer {
currentStatus = currentStatus.mapRegisters(r => r.changeY(_ - 1)).changeNZFromY currentStatus = currentStatus.mapRegisters(r => r.changeY(_ - 1)).changeNZFromY
case AssemblyLine(DEY, Implied, _, _) => case AssemblyLine(DEY, Implied, _, _) =>
currentStatus = currentStatus.mapRegisters(r => r.changeY(_ - 1)).changeNZFromY currentStatus = currentStatus.mapRegisters(r => r.changeY(_ - 1)).changeNZFromY
case AssemblyLine(INC, Implied, _, _) =>
currentStatus = currentStatus.mapRegisters(r => r.changeA(_ - 1)).changeNZFromA
case AssemblyLine(DEC, Implied, _, _) =>
currentStatus = currentStatus.mapRegisters(r => r.changeA(_ - 1)).changeNZFromA
case AssemblyLine(TAX, _, _, _) => case AssemblyLine(TAX, _, _, _) =>
currentStatus = currentStatus.mapRegisters(r => r.copy(x = r.a).afterTransfer(RegEquality.AX)).changeNZFromX currentStatus = currentStatus.mapRegisters(r => r.copy(x = r.a).afterTransfer(RegEquality.AX)).changeNZFromX
case AssemblyLine(TXA, _, _, _) => case AssemblyLine(TXA, _, _, _) =>