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Add immediate addressing mode for short branches and BRK to support some ugly tricks
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@ -13,6 +13,9 @@ There are two ways to include raw assembly code in your Millfork programs:
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Millfork inline assembly uses the same three-letter opcodes as most other 6502 assemblers.
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Indexing syntax is also the same. Only instructions available on the current CPU architecture are available.
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The short branching instructions and the `BRK` instruction support the immediate addressing mode,
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for more control over code generation.
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The `BBRn/BBSn/SMBn/RMBn` instructions cannot parameterize the tested bit. The syntax is as follows:
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BBR1 $10,label
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@ -136,6 +136,10 @@ object CoarseFlowAnalyzer {
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case AssemblyLine0(op, Implied, _) if FlowAnalyzerForImplied.hasDefinition(op) =>
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currentStatus = FlowAnalyzerForImplied.get(op)(currentStatus)
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case AssemblyLine0(op, Immediate, _) if OpcodeClasses.ShortBranching(op) =>
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// don't even both optimizing functions with weird jumps, it's futile
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return cache.put(code, List.fill[CpuStatus](code.length)(initialStatus))
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case AssemblyLine0(op, Immediate | WordImmediate, NumericConstant(nn, _)) if FlowAnalyzerForImmediate.hasDefinition(op) =>
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currentStatus = FlowAnalyzerForImmediate.get(op)(nn.toInt, currentStatus)
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@ -172,6 +172,8 @@ object ReverseFlowAnalyzer {
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case _ => false
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}
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currentImportance = if (labelIndex < 0) finalImportance else importanceArray(labelIndex) ~ currentImportance
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case AssemblyLine0(opcode, Immediate, _) if OpcodeClasses.ShortConditionalBranching(opcode) =>
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currentImportance = finalImportance
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case AssemblyLine0(opcode, ZeroPageWithRelative, StructureConstant(_, List(_, MemoryAddressConstant(Label(l))))) if OpcodeClasses.SingleBitBranch(opcode) =>
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val L = l
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val labelIndex = codeArray.indexWhere {
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@ -397,6 +397,7 @@ object MosAssembler {
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op(BEQ, Relative, 0xF0)
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op(BRK, Implied, 0)
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op(BRK, Immediate, 0)
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op(CMP, Immediate, 0xC9)
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op(CMP, ZeroPage, 0xC5)
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