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6502: Optimizations for certain byte additions (#50)
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@ -501,6 +501,14 @@ object LaterOptimizations {
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(Elidable & HasOpcode(LDA) & MatchParameter(0) & MatchAddrMode(1)) ~~>{ code =>
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code.init :+ AssemblyLine.implied(TYA).pos(code.last.source)
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},
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((HasOpcode(STA) & HasAddrModeIn(Absolute, LongAbsolute, ZeroPage) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & DoesntChangeMemoryAt(0, 1) & Not(ChangesA)).*).capture(4) ~
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(Elidable & HasOpcode(LDA) & DoesntMatterWhatItDoesWith(State.N, State.Z) & MatchAddrMode(2) & MatchParameter(3)).capture(66) ~
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((Linear & DoesntChangeMemoryAt(0, 1) & DoesntChangeMemoryAt(2, 3) & DoesntChangeIndexingInAddrMode(2) & Not(ConcernsA)).*).capture(5) ~
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(Elidable & HasOpcodeIn(ADC, ORA, EOR, AND) & HasAddrModeIn(Absolute, LongAbsolute, ZeroPage) & MatchParameter(1)) ~~> { (code, ctx) =>
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ctx.get[List[AssemblyLine]](4) ++ ctx.get[List[AssemblyLine]](5) ++ ctx.get[List[AssemblyLine]](66).map(_.copy(opcode = code.last.opcode))
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},
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)
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val DontUseIndexRegisters = new RuleBasedAssemblyOptimization("Don't use index registers unnecessarily",
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@ -1505,7 +1505,7 @@ object BuiltIns {
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AssemblyLine.implied(CLC),
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AssemblyLine.absolute(JSR, ctx.env.get[ThingInMemory]("__adc_decimal"))
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)) ++ storeLhs
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} else if (!subtract && simplicity(env, v) > simplicity(env, addend)) {
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} else if (!subtract && simplicity(env, v) >= simplicity(env, addend)) {
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val loadRhs = MosExpressionCompiler.compile(ctx, addend, Some(b -> RegisterVariable(MosRegister.A, b)), NoBranching)
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val modifyAcc = insertBeforeLast(AssemblyLine.implied(CLC), simpleOperation(ADC, ctx, v, IndexChoice.PreferY, preserveA = true, commutative = true, decimal = decimal))
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val storeLhs = MosExpressionCompiler.compileByteStorage(ctx, MosRegister.A, v)
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