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8080: Don't change BC/DE when not allowed to

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Karol Stasiak
2018-12-28 11:38:52 +01:00
parent 588d52ca80
commit 0dc16e9af2
1 changed files with 13 additions and 3 deletions
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16
src/main/scala/millfork/assembly/z80/opt/ChangeRegisterPair.scala
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@@ -1,6 +1,6 @@
package millfork.assembly.z80.opt package millfork.assembly.z80.opt
import millfork.assembly.{AssemblyOptimization, OptimizationContext} import millfork.assembly.{AssemblyOptimization, Elidability, OptimizationContext}
import millfork.assembly.z80._ import millfork.assembly.z80._
import millfork.env.{AssemblyParamSignature, NormalFunction, NormalParamSignature} import millfork.env.{AssemblyParamSignature, NormalFunction, NormalParamSignature}
import millfork.error.Logger import millfork.error.Logger
@@ -48,11 +48,11 @@ class ChangeRegisterPair(preferBC2DE: Boolean) extends AssemblyOptimization[ZLin
if (f.params.isInstanceOf[AssemblyParamSignature]) return code if (f.params.isInstanceOf[AssemblyParamSignature]) return code
val usesBC = code.exists(l => (l.readsRegister(BC) || l.changesRegister(BC)) && l.opcode != CALL) val usesBC = code.exists(l => (l.readsRegister(BC) || l.changesRegister(BC)) && l.opcode != CALL)
val usesDE = code.exists(l => (l.readsRegister(DE) || l.changesRegister(DE)) && l.opcode != CALL) val usesDE = code.exists(l => (l.readsRegister(DE) || l.changesRegister(DE)) && l.opcode != CALL)
val canDE2BC = f.returnType.size < 3 && canOptimize(code, DE2BC, Loaded()) && (f.params match { val canDE2BC = f.returnType.size < 3 && canOptimize(code, DE2BC, Loaded()) && canOptimize2(code, DE2BC) && (f.params match {
case NormalParamSignature(List(p)) => p.typ.size < 3 case NormalParamSignature(List(p)) => p.typ.size < 3
case _ => true case _ => true
}) })
val canBC2DE = canOptimize(code, BC2DE, Loaded()) val canBC2DE = canOptimize(code, BC2DE, Loaded()) && canOptimize2(code, BC2DE)
implicit val log: Logger = optimizationContext.log implicit val log: Logger = optimizationContext.log
(canDE2BC, canBC2DE) match { (canDE2BC, canBC2DE) match {
case (false, false) => code case (false, false) => code
@@ -124,6 +124,16 @@ class ChangeRegisterPair(preferBC2DE: Boolean) extends AssemblyOptimization[ZLin
case _ => true case _ => true
} }
private def canOptimize2(code: List[ZLine], dir: PairDirection): Boolean = code match {
case ZLine0(CALL, _, _) :: xs => canOptimize2(xs, dir)
case x :: xs if dir == DE2BC && (x.readsRegister(DE) || x.changesRegister(DE)) =>
(x.elidability == Elidability.Elidable || x.elidability == Elidability.Volatile) && canOptimize2(xs, dir)
case x :: xs if dir == BC2DE && (x.readsRegister(BC) || x.changesRegister(BC)) =>
(x.elidability == Elidability.Elidable || x.elidability == Elidability.Volatile) && canOptimize2(xs, dir)
case x :: xs => canOptimize2(xs, dir)
case Nil => true
}
private def switchBC2DE(code: List[ZLine]): List[ZLine] = { private def switchBC2DE(code: List[ZLine]): List[ZLine] = {
code match { code match {
case (x@ZLine0(_, OneRegister(B), _)) :: xs => case (x@ZLine0(_, OneRegister(B), _)) :: xs =>