mirror of
https://github.com/KarolS/millfork.git
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Fix stack overflow
This commit is contained in:
Karol Stasiak
parent
51599c9615
commit
14d6cf4d5c
@ -5,6 +5,8 @@ import millfork.assembly.{AssemblyOptimization, Elidability, OptimizationContext
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import millfork.env.NormalFunction
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import millfork.error.Logger
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import scala.util.control.TailCalls.{TailRec, done, tailcall}
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/**
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* @author Karol Stasiak
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*/
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@ -58,14 +60,14 @@ class ChangeIndexRegisterOptimization(preferX2Y: Boolean) extends AssemblyOptimi
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case (true, false) =>
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if (!usesX) code else {
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log.debug("Changing index register from X to Y")
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val changed = switchX2Y(code)
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val changed = switchX2Y(code).result
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traceDiff(code, changed)
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changed
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}
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case (false, true) =>
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if (!usesY) code else {
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log.debug("Changing index register from Y to X")
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val changed = switchY2X(code)
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val changed = switchY2X(code).result
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traceDiff(code, changed)
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changed
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}
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@ -73,14 +75,14 @@ class ChangeIndexRegisterOptimization(preferX2Y: Boolean) extends AssemblyOptimi
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if (preferX2Y) {
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if (!usesX) code else {
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log.debug("Changing index register from X to Y (arbitrarily)")
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val changed = switchX2Y(code)
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val changed = switchX2Y(code).result
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traceDiff(code, changed)
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changed
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}
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} else {
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if (!usesY) code else {
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log.debug("Changing index register from Y to X (arbitrarily)")
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val changed = switchY2X(code)
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val changed = switchY2X(code).result
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traceDiff(code, changed)
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changed
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}
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@ -160,32 +162,32 @@ class ChangeIndexRegisterOptimization(preferX2Y: Boolean) extends AssemblyOptimi
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case Nil => true
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}
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private def switchX2Y(code: List[AssemblyLine])(implicit log: Logger): List[AssemblyLine] = code match {
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private def switchX2Y(code: List[AssemblyLine])(implicit log: Logger): TailRec[List[AssemblyLine]] = code match {
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (b@AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | LDY | STY | STZ, AbsoluteX | ZeroPageX, _))
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:: xs => a :: b :: switchX2Y(xs)
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:: xs => tailcall(switchX2Y(xs)).map(a :: b :: _)
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (b@AssemblyLine0(_, IndexedX, _))
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:: xs => a :: b :: switchX2Y(xs)
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:: xs => tailcall(switchX2Y(xs)).map(a :: b :: _)
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (i@AssemblyLine0(INX | DEX, _, _))
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:: (b@AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | LDY | STY | STZ, AbsoluteX | ZeroPageX, _))
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:: xs => a :: i :: b :: switchX2Y(xs)
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:: xs => tailcall(switchX2Y(xs)).map(a :: i :: b :: _)
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (i@AssemblyLine0(INX | DEX, _, _))
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:: (b@AssemblyLine0(_, IndexedX, _))
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:: xs => a :: i :: b :: switchX2Y(xs)
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case (x@AssemblyLine0(TAX, _, _)) :: xs => x.copy(opcode = TAY) :: switchX2Y(xs)
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case (x@AssemblyLine0(TXA, _, _)) :: xs => x.copy(opcode = TYA) :: switchX2Y(xs)
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case (x@AssemblyLine0(TXY | TYX, _, _)) :: xs => x.copy(opcode = TYX) :: switchX2Y(xs) // keep the transfer for the flags
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case (x@AssemblyLine0(STX, _, _)) :: xs => x.copy(opcode = STY) :: switchX2Y(xs)
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case (x@AssemblyLine0(LDX, _, _)) :: xs => x.copy(opcode = LDY) :: switchX2Y(xs)
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case (x@AssemblyLine0(INX, _, _)) :: xs => x.copy(opcode = INY) :: switchX2Y(xs)
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case (x@AssemblyLine0(DEX, _, _)) :: xs => x.copy(opcode = DEY) :: switchX2Y(xs)
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case (x@AssemblyLine0(CPX, _, _)) :: xs => x.copy(opcode = CPY) :: switchX2Y(xs)
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case (x@AssemblyLine0(PHX, _, _)) :: xs => x.copy(opcode = PHY) :: switchX2Y(xs)
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case (x@AssemblyLine0(PLX, _, _)) :: xs => x.copy(opcode = PLY) :: switchX2Y(xs)
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case (x@AssemblyLine0(HuSAX, _, _)) :: xs => x.copy(opcode = SAY) :: switchX2Y(xs)
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:: xs => tailcall(switchX2Y(xs)).map(a :: i :: b :: _)
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case (x@AssemblyLine0(TAX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = TAY) :: _)
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case (x@AssemblyLine0(TXA, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = TYA) :: _)
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case (x@AssemblyLine0(TXY | TYX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = TYX) :: _) // keep the transfer for the flags
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case (x@AssemblyLine0(STX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = STY) :: _)
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case (x@AssemblyLine0(LDX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = LDY) :: _)
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case (x@AssemblyLine0(INX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = INY) :: _)
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case (x@AssemblyLine0(DEX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = DEY) :: _)
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case (x@AssemblyLine0(CPX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = CPY) :: _)
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case (x@AssemblyLine0(PHX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = PHY) :: _)
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case (x@AssemblyLine0(PLX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = PLY) :: _)
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case (x@AssemblyLine0(HuSAX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = SAY) :: _)
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case AssemblyLine0(LAX, _, _) :: xs => log.fatal("Unexpected LAX")
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case AssemblyLine0(TXS, _, _) :: xs => log.fatal("Unexpected TXS")
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@ -194,42 +196,42 @@ class ChangeIndexRegisterOptimization(preferX2Y: Boolean) extends AssemblyOptimi
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case AssemblyLine0(SAX, _, _) :: xs => log.fatal("Unexpected SAX")
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case AssemblyLine0(SXY, _, _) :: xs => log.fatal("Unexpected SXY")
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case (x@AssemblyLine0(_, AbsoluteX, _)) :: xs => x.copy(addrMode = AbsoluteY) :: switchX2Y(xs)
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case (x@AssemblyLine0(_, ZeroPageX, _)) :: xs => x.copy(addrMode = ZeroPageY) :: switchX2Y(xs)
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case (x@AssemblyLine0(_, AbsoluteX, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(addrMode = AbsoluteY) :: _)
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case (x@AssemblyLine0(_, ZeroPageX, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(addrMode = ZeroPageY) :: _)
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case (x@AssemblyLine0(_, IndexedX, _)) :: xs => log.fatal("Unexpected IndexedX")
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case x::xs => x :: switchX2Y(xs)
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case Nil => Nil
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case x::xs => tailcall(switchX2Y(xs)).map(x :: _)
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case Nil => done(Nil)
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}
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private def switchY2X(code: List[AssemblyLine])(implicit log: Logger): List[AssemblyLine] = code match {
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private def switchY2X(code: List[AssemblyLine])(implicit log: Logger): TailRec[List[AssemblyLine]] = code match {
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case AssemblyLine0(LDY | TAY, _, _)
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:: AssemblyLine0(_, IndexedY, _)
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:: xs => code.take(2) ++ switchY2X(xs)
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:: xs => tailcall(switchY2X(xs)).map(code.take(2) ++ _)
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case AssemblyLine0(LDY | TAY, _, _)
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:: (i@AssemblyLine0(INY | DEY, _, _))
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:: AssemblyLine0(_, IndexedY, _)
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:: xs => code.take(3) ++ switchY2X(xs)
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case (x@AssemblyLine0(TAY, _, _)) :: xs => x.copy(opcode = TAX) :: switchY2X(xs)
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case (x@AssemblyLine0(TYA, _, _)) :: xs => x.copy(opcode = TXA) :: switchY2X(xs)
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case (x@AssemblyLine0(TYX | TXY, _, _)) :: xs => x.copy(opcode = TXY) :: switchY2X(xs) // keep the transfer for the flags
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case (x@AssemblyLine0(STY, _, _)) :: xs => x.copy(opcode = STX) :: switchY2X(xs)
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case (x@AssemblyLine0(LDY, _, _)) :: xs => x.copy(opcode = LDX) :: switchY2X(xs)
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case (x@AssemblyLine0(INY, _, _)) :: xs => x.copy(opcode = INX) :: switchY2X(xs)
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case (x@AssemblyLine0(DEY, _, _)) :: xs => x.copy(opcode = DEX) :: switchY2X(xs)
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case (x@AssemblyLine0(CPY, _, _)) :: xs => x.copy(opcode = CPX) :: switchY2X(xs)
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case (x@AssemblyLine0(PHY, _, _)) :: xs => x.copy(opcode = PHX) :: switchY2X(xs)
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case (x@AssemblyLine0(PLY, _, _)) :: xs => x.copy(opcode = PLX) :: switchY2X(xs)
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case (x@AssemblyLine0(SAY, _, _)) :: xs => x.copy(opcode = HuSAX) :: switchY2X(xs)
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:: xs => tailcall(switchY2X(xs)).map(code.take(3) ++ _)
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case (x@AssemblyLine0(TAY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = TAX) :: _)
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case (x@AssemblyLine0(TYA, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = TXA) :: _)
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case (x@AssemblyLine0(TYX | TXY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = TXY) :: _) // keep the transfer for the flags
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case (x@AssemblyLine0(STY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = STX) :: _)
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case (x@AssemblyLine0(LDY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = LDX) :: _)
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case (x@AssemblyLine0(INY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = INX) :: _)
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case (x@AssemblyLine0(DEY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = DEX) :: _)
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case (x@AssemblyLine0(CPY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = CPX) :: _)
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case (x@AssemblyLine0(PHY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = PHX) :: _)
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case (x@AssemblyLine0(PLY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = PLX) :: _)
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case (x@AssemblyLine0(SAY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = HuSAX) :: _)
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case AssemblyLine0(SXY, _, _) :: xs => log.fatal("Unexpected SXY")
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case (x@AssemblyLine0(_, AbsoluteY, _)) :: xs => x.copy(addrMode = AbsoluteX) :: switchY2X(xs)
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case (x@AssemblyLine0(_, ZeroPageY, _)) :: xs => x.copy(addrMode = ZeroPageX) :: switchY2X(xs)
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case (x@AssemblyLine0(_, AbsoluteY, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(addrMode = AbsoluteX) :: _)
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case (x@AssemblyLine0(_, ZeroPageY, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(addrMode = ZeroPageX) :: _)
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case AssemblyLine0(_, IndexedY, _) :: xs => log.fatal("Unexpected IndexedY")
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case AssemblyLine0(_, LongIndexedY, _) :: xs => log.fatal("Unexpected LongIndexedY")
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case AssemblyLine0(_, IndexedSY, _) :: xs => log.fatal("Unexpected IndexedSY")
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case x::xs => x :: switchY2X(xs)
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case Nil => Nil
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case x::xs => tailcall(switchY2X(xs)).map(x :: _)
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case Nil => done(Nil)
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}
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}
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