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6502: Better passing of register parameters
This commit is contained in:
Karol Stasiak
parent
25ca2cd6b8
commit
19c0668002
@ -426,6 +426,15 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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case 2 =>
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AssemblyLine.variable(ctx, LDX, source) ++ AssemblyLine.variable(ctx,LDA, source, 1)
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}
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case RegisterVariable(MosRegister.XY, _) =>
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exprType.size match {
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case 1 => if (exprType.isSigned) {
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AssemblyLine.variable(ctx, LDX, source) ++ List(AssemblyLine.implied(TXA)) ++ signExtendA(ctx) ++ List(AssemblyLine.implied(TAY))
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} else
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AssemblyLine.variable(ctx, LDX, source) :+ AssemblyLine.immediate(LDY, 0)
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case 2 =>
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AssemblyLine.variable(ctx, LDX, source) ++ AssemblyLine.variable(ctx, LDY, source, 1)
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}
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case RegisterVariable(MosRegister.YA, _) =>
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exprType.size match {
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case 1 => if (exprType.isSigned) {
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@ -435,6 +444,15 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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case 2 =>
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AssemblyLine.variable(ctx, LDY, source) ++ AssemblyLine.variable(ctx, LDA, source, 1)
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}
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case RegisterVariable(MosRegister.YX, _) =>
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exprType.size match {
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case 1 => if (exprType.isSigned) {
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AssemblyLine.variable(ctx, LDY, source) ++ List(AssemblyLine.implied(TYA)) ++ signExtendA(ctx) ++ List(AssemblyLine.implied(TAX))
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} else
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AssemblyLine.variable(ctx, LDY, source) :+ AssemblyLine.immediate(LDX, 0)
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case 2 =>
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AssemblyLine.variable(ctx, LDY, source) ++ AssemblyLine.variable(ctx, LDX, source, 1)
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}
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case target: VariableInMemory =>
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if (exprType.size > target.typ.size) {
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ctx.log.error(s"Variable `$target.name` is too small", expr.position)
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@ -497,8 +515,11 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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case RegisterVariable(MosRegister.AY, _) =>
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AssemblyLine.tsx(ctx) ++ (exprType.size match {
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case 1 => if (exprType.isSigned) {
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val label = ctx.nextLabel("sx")
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??? // TODO
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(PHA)) ++
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signExtendA(ctx) ++
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List(AssemblyLine.implied(PLA))
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} else {
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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@ -509,12 +530,30 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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AssemblyLine.dataStackX(ctx, LDY, offset + 1))
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})
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case RegisterVariable(MosRegister.XA, _) =>
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??? // TODO
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AssemblyLine.tsx(ctx) ++ (exprType.size match {
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case 1 => if (exprType.isSigned) {
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(TAX)) ++
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signExtendA(ctx)
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} else {
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(TAX),
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AssemblyLine.immediate(LDA, 0))
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}
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case 2 => List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.dataStackX(ctx, LDY, offset + 1),
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AssemblyLine.implied(TAX),
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AssemblyLine.implied(TYA))
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})
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case RegisterVariable(MosRegister.YA, _) =>
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AssemblyLine.tsx(ctx) ++ (exprType.size match {
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case 1 => if (exprType.isSigned) {
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val label = ctx.nextLabel("sx")
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??? // TODO
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(TAY)) ++ signExtendA(ctx)
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} else {
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List(
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AssemblyLine.dataStackX(ctx, LDY, offset),
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@ -524,6 +563,43 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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AssemblyLine.dataStackX(ctx, LDY, offset),
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AssemblyLine.dataStackX(ctx, LDA, offset + 1))
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})
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case RegisterVariable(MosRegister.YX, _) =>
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AssemblyLine.tsx(ctx) ++ (exprType.size match {
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case 1 => if (exprType.isSigned) {
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(TAY)) ++
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signExtendA(ctx) ++
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List(AssemblyLine.implied(TAX))
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} else {
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List(
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AssemblyLine.dataStackX(ctx, LDY, offset),
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AssemblyLine.immediate(LDX, 0))
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}
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case 2 => List(
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AssemblyLine.dataStackX(ctx, LDY, offset),
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AssemblyLine.dataStackX(ctx, LDA, offset + 1),
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AssemblyLine.implied(TAX))
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})
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case RegisterVariable(MosRegister.XY, _) =>
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AssemblyLine.tsx(ctx) ++ (exprType.size match {
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case 1 => if (exprType.isSigned) {
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(TAX)) ++
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signExtendA(ctx) ++
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List(AssemblyLine.implied(TAY))
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} else {
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List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.implied(TAX),
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AssemblyLine.immediate(LDY, 0))
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}
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case 2 => List(
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AssemblyLine.dataStackX(ctx, LDA, offset),
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AssemblyLine.dataStackX(ctx, LDY, offset + 1),
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AssemblyLine.implied(TAX))
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})
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case target: VariableInMemory =>
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if (exprType.size > target.typ.size) {
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ctx.log.error(s"Variable `$target.name` is too small", expr.position)
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@ -714,11 +790,17 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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compile(ctx, l, Some(b -> RegisterVariable(MosRegister.A, b)), branches) ++
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preserveRegisterIfNeeded(ctx, MosRegister.A, compile(ctx, h, Some(b -> RegisterVariable(MosRegister.Y, b)), branches))
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case RegisterVariable(MosRegister.XA, _) =>
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compile(ctx, l, Some(b -> RegisterVariable(MosRegister.X, b)), branches) ++
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compile(ctx, h, Some(b -> RegisterVariable(MosRegister.A, b)), branches)
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compile(ctx, h, Some(b -> RegisterVariable(MosRegister.A, b)), branches) ++
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preserveRegisterIfNeeded(ctx, MosRegister.A, compile(ctx, l, Some(b -> RegisterVariable(MosRegister.X, b)), branches))
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case RegisterVariable(MosRegister.YA, _) =>
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compile(ctx, h, Some(b -> RegisterVariable(MosRegister.A, b)), branches) ++
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preserveRegisterIfNeeded(ctx, MosRegister.A, compile(ctx, l, Some(b -> RegisterVariable(MosRegister.Y, b)), branches))
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case RegisterVariable(MosRegister.XY, _) =>
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compile(ctx, l, Some(b -> RegisterVariable(MosRegister.X, b)), branches) ++
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preserveRegisterIfNeeded(ctx, MosRegister.X, compile(ctx, h, Some(b -> RegisterVariable(MosRegister.Y, b)), branches))
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case RegisterVariable(MosRegister.YX, _) =>
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compile(ctx, l, Some(b -> RegisterVariable(MosRegister.Y, b)), branches) ++
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compile(ctx, h, Some(b -> RegisterVariable(MosRegister.A, b)), branches)
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preserveRegisterIfNeeded(ctx, MosRegister.Y, compile(ctx, h, Some(b -> RegisterVariable(MosRegister.X, b)), branches))
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case target: VariableInMemory =>
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target.typ.size match {
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case 1 =>
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@ -1172,10 +1254,14 @@ object MosExpressionCompiler extends AbstractExpressionCompiler[AssemblyLine] {
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}
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val thirdViaRegisters = pairs.flatMap {
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case (paramExpr, AssemblyParam(typ, paramVar@RegisterVariable(register, _), AssemblyParameterPassingBehaviour.Copy)) =>
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compile(ctx, paramExpr, Some(typ -> paramVar), NoBranching)
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// TODO: fix
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Some(register -> compile(ctx, paramExpr, Some(typ -> paramVar), NoBranching))
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case _ => Nil
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} match {
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case Seq() => Nil
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case Seq((_, param)) => param
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case Seq((MosRegister.A, pa), (_, pxy)) => pa ++ preserveRegisterIfNeeded(ctx, MosRegister.A, pxy)
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case Seq((_, pxy), (MosRegister.A, pa)) => pa ++ preserveRegisterIfNeeded(ctx, MosRegister.A, pxy)
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case other => other.flatMap(_._2) // TODO : make sure all registers are passed in correctly
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}
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secondViaMemory ++ thirdViaRegisters :+ AssemblyLine.absoluteOrLongAbsolute(JSR, function, ctx.options)
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case NormalParamSignature(List(MemoryVariable(_, typ, _))) if typ.size == 1 =>
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