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8080: Exchange BC/DE registers pairs
This commit is contained in:
Karol Stasiak
parent
e66e938469
commit
1c55304bad
@ -0,0 +1,222 @@
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package millfork.assembly.z80.opt
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import millfork.assembly.{AssemblyOptimization, OptimizationContext}
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import millfork.assembly.z80._
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import millfork.env.{AssemblyParamSignature, NormalFunction, NormalParamSignature}
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import millfork.error.Logger
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import millfork.node.ZRegister
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/**
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* @author Karol Stasiak
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*/
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object ChangeRegisterPairPreferringDE extends ChangeRegisterPair(true)
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object ChangeRegisterPairPreferringBC extends ChangeRegisterPair(false)
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class ChangeRegisterPair(preferBC2DE: Boolean) extends AssemblyOptimization[ZLine] {
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import millfork.node.ZRegister._
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case class Loaded(b: Boolean = false, c: Boolean = false, d: Boolean = false, e: Boolean = false) {
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def load(register: ZRegister.Value): Loaded = register match {
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case B => copy(b = true, d = false, e = false)
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case C => copy(c = true, d = false, e = false)
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case BC => Loaded(b = true, c = true)
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case D => copy(d = true, b = false, c = false)
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case E => copy(e = true, b = false, c = false)
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case DE => Loaded(d = true, e = true)
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case _ => this
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}
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def hasDE: Boolean = d && e
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def hasBC: Boolean = b && c
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}
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object PairDirection extends Enumeration {
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val BC2DE, DE2BC = Value
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}
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import PairDirection._
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import millfork.assembly.z80.ZOpcode._
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type PairDirection = PairDirection.Value
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override def name = "Changing registers pairs"
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override def optimize(f: NormalFunction, code: List[ZLine], optimizationContext: OptimizationContext): List[ZLine] = {
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if (f.params.isInstanceOf[AssemblyParamSignature]) return code
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val usesBC = code.exists(l => (l.readsRegister(BC) || l.changesRegister(BC)) && l.opcode != CALL)
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val usesDE = code.exists(l => (l.readsRegister(DE) || l.changesRegister(DE)) && l.opcode != CALL)
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val canDE2BC = f.returnType.size < 3 && canOptimize(code, DE2BC, Loaded()) && (f.params match {
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case NormalParamSignature(List(p)) => p.typ.size < 3
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case _ => true
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})
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val canBC2DE = canOptimize(code, BC2DE, Loaded())
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implicit val log: Logger = optimizationContext.log
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(canDE2BC, canBC2DE) match {
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case (false, false) => code
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case (true, false) =>
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if (!usesDE) code else {
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log.debug("Changing register pair from DE to BC")
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val changed = switchDE2BC(code)
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traceDiff(code, changed)
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changed
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}
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case (false, true) =>
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if (!usesBC) code else {
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log.debug("Changing register pair from BC to DE")
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val changed = switchBC2DE(code)
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traceDiff(code, changed)
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changed
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}
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case (true, true) =>
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if (preferBC2DE) {
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if (!usesBC) code else {
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log.debug("Changing register pair from BC to DE (arbitrarily)")
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val changed = switchBC2DE(code)
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traceDiff(code, changed)
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changed
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}
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} else {
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if (!usesDE) code else {
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log.debug("Changing register pair from DE to BC (arbitrarily)")
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val changed = switchDE2BC(code)
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traceDiff(code, changed)
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changed
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}
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}
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}
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}
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private def traceDiff(original: List[ZLine], changed: List[ZLine])(implicit log: Logger): Unit = {
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if (log.traceEnabled) {
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original.zip(changed).foreach {
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case (o, n) =>
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if (o.registers == n.registers && o.opcode == n.opcode) log.trace(n.toString)
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else log.trace(f"$o%-30s → $n%s")
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}
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}
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}
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private def canOptimize(code: List[ZLine], dir: PairDirection, loaded: Loaded): Boolean = code match {
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case ZLine0(CALL, _, _) :: xs => false // TODO
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case ZLine0(LD_16, TwoRegisters(r, IMM_16), _) :: xs => canOptimize(xs, dir, loaded = loaded.load(r))
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case ZLine0(LD,
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TwoRegisters(B, C) |
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TwoRegisters(B, E) |
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TwoRegisters(C, B) |
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TwoRegisters(C, D) |
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TwoRegisters(D, E) |
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TwoRegisters(D, C) |
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TwoRegisters(E, D) |
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TwoRegisters(E, B), _) :: xs => false
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case ZLine0(LD, TwoRegisters(r@(B|C|D|E), _), _) :: xs => canOptimize(xs, dir, loaded = loaded.load(r))
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case ZLine0(LD, TwoRegistersOffset(r@(B|C|D|E), _, _), _) :: xs => canOptimize(xs, dir, loaded = loaded.load(r))
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case ZLine0(LABEL | CALL | JR | JP, _, _) :: xs => canOptimize(xs, dir, loaded = Loaded())
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case ZLine0(EX_DE_HL, _, _) :: xs => if (loaded.hasDE && dir == BC2DE) canOptimize(xs, dir, loaded) else false
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case ZLine0(DJNZ, _, _) :: xs => if (loaded.b && dir == DE2BC) canOptimize(xs, dir, loaded) else false
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case x :: xs if !loaded.b && (x.readsRegister(B) || x.changesRegister(B)) => false
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case x :: xs if !loaded.c && (x.readsRegister(C) || x.changesRegister(C)) => false
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case x :: xs if !loaded.d && (x.readsRegister(D) || x.changesRegister(D)) => false
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case x :: xs if !loaded.e && (x.readsRegister(E) || x.changesRegister(E)) => false
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case x :: xs => canOptimize(xs, dir, loaded)
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case _ => true
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}
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private def switchBC2DE(code: List[ZLine]): List[ZLine] = {
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code match {
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case (x@ZLine0(_, OneRegister(B), _)) :: xs =>
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x.copy(registers = OneRegister(D)) :: switchBC2DE(xs)
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case (x@ZLine0(_, OneRegister(C), _)) :: xs =>
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x.copy(registers = OneRegister(E)) :: switchBC2DE(xs)
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case (x@ZLine0(_, OneRegister(BC), _)) :: xs =>
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x.copy(registers = OneRegister(DE)) :: switchBC2DE(xs)
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case (x@ZLine0(LD, TwoRegisters(B, D), _)) :: xs =>
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switchBC2DE(xs)
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case (x@ZLine0(LD, TwoRegisters(C, E), _)) :: xs =>
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switchBC2DE(xs)
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case (x@ZLine0(LD, TwoRegisters(D, B), _)) :: xs =>
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switchBC2DE(xs)
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case (x@ZLine0(LD, TwoRegisters(E, C), _)) :: xs =>
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switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegisters(BC, r), _)) :: xs =>
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x.copy(registers = TwoRegisters(DE, r)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegisters(r, BC), _)) :: xs =>
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x.copy(registers = TwoRegisters(r, DE)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegisters(B, r), _)) :: xs =>
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x.copy(registers = TwoRegisters(D, r)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegisters(r, B), _)) :: xs =>
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x.copy(registers = TwoRegisters(r, D)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegisters(C, r), _)) :: xs =>
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x.copy(registers = TwoRegisters(E, r)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegisters(r, C), _)) :: xs =>
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x.copy(registers = TwoRegisters(r, E)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegistersOffset(B, r, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(D, r, o)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegistersOffset(r, B, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(r, D, o)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegistersOffset(C, r, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(E, r, o)) :: switchBC2DE(xs)
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case (x@ZLine0(_, TwoRegistersOffset(r, C, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(r, E, o)) :: switchBC2DE(xs)
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case x :: xs => x :: switchBC2DE(xs)
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case Nil => Nil
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}
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}
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private def switchDE2BC(code: List[ZLine]): List[ZLine] = {
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code match {
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case (x@ZLine0(_, OneRegister(D), _)) :: xs =>
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x.copy(registers = OneRegister(B)) :: switchDE2BC(xs)
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case (x@ZLine0(_, OneRegister(E), _)) :: xs =>
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x.copy(registers = OneRegister(C)) :: switchDE2BC(xs)
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case (x@ZLine0(_, OneRegister(BC), _)) :: xs =>
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x.copy(registers = OneRegister(DE)) :: switchDE2BC(xs)
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case (x@ZLine0(LD, TwoRegisters(B, D), _)) :: xs =>
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switchBC2DE(xs)
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case (x@ZLine0(LD, TwoRegisters(C, E), _)) :: xs =>
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switchBC2DE(xs)
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case (x@ZLine0(LD, TwoRegisters(D, B), _)) :: xs =>
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switchDE2BC(xs)
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case (x@ZLine0(LD, TwoRegisters(E, C), _)) :: xs =>
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switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegisters(DE, r), _)) :: xs =>
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x.copy(registers = TwoRegisters(BC, r)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegisters(r, DE), _)) :: xs =>
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x.copy(registers = TwoRegisters(r, BC)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegisters(D, r), _)) :: xs =>
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x.copy(registers = TwoRegisters(B, r)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegisters(r, D), _)) :: xs =>
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x.copy(registers = TwoRegisters(r, B)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegisters(E, r), _)) :: xs =>
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x.copy(registers = TwoRegisters(C, r)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegisters(r, E), _)) :: xs =>
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x.copy(registers = TwoRegisters(r, C)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegistersOffset(D, r, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(B, r, o)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegistersOffset(r, D, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(r, B, o)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegistersOffset(E, r, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(C, r, o)) :: switchDE2BC(xs)
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case (x@ZLine0(_, TwoRegistersOffset(r, E, o), _)) :: xs =>
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x.copy(registers = TwoRegistersOffset(r, C, o)) :: switchDE2BC(xs)
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case x :: xs => x :: switchBC2DE(xs)
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case Nil => Nil
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}
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}
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}
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@ -50,6 +50,8 @@ object VariableLifetime {
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}
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}
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// val log = new ConsoleLogger
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// log.verbosity = 3
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// log.trace("Lifetime for " + variableName)
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// codeWithFlow.zipWithIndex.foreach {
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// case ((_, line), index) =>
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@ -17,7 +17,7 @@ object Z80OptimizationPresets {
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EmptyParameterStoreRemoval,
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EmptyMemoryStoreRemoval)
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).flatten ++
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List(WordVariableToRegisterOptimization, ByteVariableToRegisterOptimization, CompactStackFrame) ++
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List(ChangeRegisterPairPreferringDE, WordVariableToRegisterOptimization, ByteVariableToRegisterOptimization, ChangeRegisterPairPreferringBC, CompactStackFrame) ++
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LaterIntel8080Optimizations.All ++ LaterI80Optimizations.All
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).flatten
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}
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@ -31,7 +31,7 @@ object Z80OptimizationPresets {
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EmptyMemoryStoreRemoval,
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)
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).flatten ++
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List(WordVariableToRegisterOptimization, ByteVariableToRegisterOptimization) ++
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List(ChangeRegisterPairPreferringDE, WordVariableToRegisterOptimization, ByteVariableToRegisterOptimization, ChangeRegisterPairPreferringBC) ++
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LaterIntel8080Optimizations.All ++ LaterI80Optimizations.All
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).flatten
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}
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@ -44,7 +44,7 @@ object Z80OptimizationPresets {
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EmptyParameterStoreRemoval,
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EmptyMemoryStoreRemoval)
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).flatten ++
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List(WordVariableToRegisterOptimization, ByteVariableToRegisterOptimization) ++
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List(ChangeRegisterPairPreferringDE, WordVariableToRegisterOptimization, ByteVariableToRegisterOptimization, ChangeRegisterPairPreferringBC) ++
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LaterSharpOptimizations.All ++ LaterI80Optimizations.All
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).flatten
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}
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