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Interrupt handler optimization fixes
This commit is contained in:
Karol Stasiak
parent
516d7eae26
commit
2548822b8b
@ -228,41 +228,50 @@ object AlwaysGoodOptimizations {
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},
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)
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private def operationPairBuilder(op1: Opcode.Value, op2: Opcode.Value, middle: AssemblyLinePattern) = {
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private def operationPairBuilder(op1: Opcode.Value, op2: Opcode.Value, middle: AssemblyLinePattern, discardToRemove: Option[Opcode.Value]) = {
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(HasOpcode(op1) & Elidable) ~
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(Linear & middle).*.capture(1) ~
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(HasOpcode(op2) & Elidable) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(2) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](1) ++ ctx.get[List[AssemblyLine]](2)
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ctx.get[List[AssemblyLine]](1).filter(l => !discardToRemove.contains(l.opcode)) ++ ctx.get[List[AssemblyLine]](2)
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}
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}
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val PointlessOperationPairRemoval = new RuleBasedAssemblyOptimization("Pointless operation pair",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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operationPairBuilder(PHA, PLA, Not(ChangesA) & Not(ConcernsStack)),
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operationPairBuilder(PHX, PLX, Not(ChangesX) & Not(ConcernsStack)),
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operationPairBuilder(PHY, PLY, Not(ChangesY) & Not(ConcernsStack)),
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operationPairBuilder(PHZ, PLZ, Not(ChangesIZ) & Not(ConcernsStack)),
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operationPairBuilder(INX, DEX, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder(DEX, INX, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder(INY, DEY, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder(DEY, INY, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder(PHA, PLA, Not(ChangesA) & Not(ConcernsStack), Some(DISCARD_AF)),
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operationPairBuilder(PHX, PLX, Not(ChangesX) & Not(ConcernsStack), Some(DISCARD_XF)),
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operationPairBuilder(PHY, PLY, Not(ChangesY) & Not(ConcernsStack), Some(DISCARD_YF)),
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operationPairBuilder(PHZ, PLZ, Not(ChangesIZ) & Not(ConcernsStack), Some(DISCARD_YF)),
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operationPairBuilder(INX, DEX, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder(DEX, INX, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder(INY, DEY, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder(DEY, INY, Not(ConcernsX) & Not(ReadsNOrZ), None),
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)
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private def operationPairBuilder2(op1: Opcode.Value, op1extra: AssemblyLinePattern, middle: AssemblyLinePattern,op2: Opcode.Value, op2extra: AssemblyLinePattern) = {
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private def operationPairBuilder2(op1: Opcode.Value, op1extra: AssemblyLinePattern, middle: AssemblyLinePattern,op2: Opcode.Value, op2extra: AssemblyLinePattern, discardToRemove: Option[Opcode.Value]) = {
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(HasOpcode(op1) & Elidable & op1extra) ~
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(Linear & middle).*.capture(1) ~
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(HasOpcode(op2) & Elidable & op2extra) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](1)
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ctx.get[List[AssemblyLine]](1).filter(l => !discardToRemove.contains(l.opcode))
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}
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}
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private def operationPairBuilder3(op1: Opcode.Value, op1extra: AssemblyLinePattern, op2: Opcode.Value, middle: AssemblyLinePattern) = {
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private def operationPairBuilder3(op1: Opcode.Value, op1extra: AssemblyLinePattern, op2: Opcode.Value, middle: AssemblyLinePattern, discardToRemove: Option[Opcode.Value]) = {
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(HasOpcode(op1) & Elidable & op1extra) ~
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middle.*.capture(1) ~
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Where(_.isExternallyLinearBlock(1)) ~
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(HasOpcode(op2) & Elidable) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](1).filter(l => !discardToRemove.contains(l.opcode))
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}
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}
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private def operationPairBuilder4(op1: Opcode.Value, op1extra: AssemblyLinePattern, middle: AssemblyLinePattern, op2: Opcode.Value, op2extra: AssemblyLinePattern) = {
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(HasOpcode(op1) & op1extra & Elidable & HasAddrModeIn(Set(Absolute, ZeroPage, LongAbsolute)) & MatchParameter(3)) ~
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middle.*.capture(1) ~
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Where(_.isExternallyLinearBlock(1)) ~
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(HasOpcode(op2) & op2extra & Elidable & HasAddrModeIn(Set(Absolute, ZeroPage, LongAbsolute)) & MatchParameter(3)) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](1)
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}
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}
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@ -272,41 +281,65 @@ object AlwaysGoodOptimizations {
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operationPairBuilder2(
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PHA, Anything,
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Not(ConcernsStack),
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PLA, DoesntMatterWhatItDoesWith(State.A, State.N, State.Z)),
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PLA, DoesntMatterWhatItDoesWith(State.A, State.N, State.Z), Some(DISCARD_AF)),
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operationPairBuilder2(
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PHX, Anything,
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Not(ConcernsStack),
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PLX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z)),
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PLX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z), Some(DISCARD_XF)),
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operationPairBuilder2(
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PHY, Anything,
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Not(ConcernsStack),
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PLY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z)),
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PLY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z), Some(DISCARD_YF)),
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operationPairBuilder2(
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INX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z),
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Anything,
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DEX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z)),
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DEX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z), None),
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operationPairBuilder2(
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DEX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z),
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Anything,
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INX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z)),
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INX, DoesntMatterWhatItDoesWith(State.X, State.N, State.Z), None),
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operationPairBuilder2(
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INY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z),
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Anything,
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DEY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z)),
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DEY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z), None),
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operationPairBuilder2(
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DEY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z),
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Anything,
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INY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z)),
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operationPairBuilder3(PHA, Anything, PLA, Not(ChangesA) & Not(ConcernsStack)),
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operationPairBuilder3(PHX, Anything, PLX, Not(ChangesX) & Not(ConcernsStack)),
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operationPairBuilder3(PHY, Anything, PLY, Not(ChangesY) & Not(ConcernsStack)),
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operationPairBuilder3(PHZ, Anything, PLZ, Not(ChangesIZ) & Not(ConcernsStack)),
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operationPairBuilder3(PHD, Anything, PLD, Not(ChangesDirectPageRegister)),
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operationPairBuilder3(PHB, Anything, PLB, Not(ChangesDataBankRegister)),
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operationPairBuilder3(INX, DoesntMatterWhatItDoesWith(State.N, State.Z), DEX, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder3(DEX, DoesntMatterWhatItDoesWith(State.N, State.Z), INX, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder3(INY, DoesntMatterWhatItDoesWith(State.N, State.Z), DEY, Not(ConcernsX) & Not(ReadsNOrZ)),
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operationPairBuilder3(DEY, DoesntMatterWhatItDoesWith(State.N, State.Z), INY, Not(ConcernsX) & Not(ReadsNOrZ)),
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INY, DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z), None),
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operationPairBuilder3(PHA, Anything, PLA, Not(ChangesA) & Not(ConcernsStack), Some(DISCARD_AF)),
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operationPairBuilder3(PHX, Anything, PLX, Not(ChangesX) & Not(ConcernsStack), Some(DISCARD_XF)),
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operationPairBuilder3(PHY, Anything, PLY, Not(ChangesY) & Not(ConcernsStack), Some(DISCARD_YF)),
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operationPairBuilder3(PHZ, Anything, PLZ, Not(ChangesIZ) & Not(ConcernsStack), Some(DISCARD_YF)),
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operationPairBuilder3(PHD, Anything, PLD, Not(ChangesDirectPageRegister), None),
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operationPairBuilder3(PHB, Anything, PLB, Not(ChangesDataBankRegister), None),
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operationPairBuilder3(INX, DoesntMatterWhatItDoesWith(State.N, State.Z), DEX, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder3(DEX, DoesntMatterWhatItDoesWith(State.N, State.Z), INX, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder3(INY, DoesntMatterWhatItDoesWith(State.N, State.Z), DEY, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder3(DEY, DoesntMatterWhatItDoesWith(State.N, State.Z), INY, Not(ConcernsX) & Not(ReadsNOrZ), None),
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operationPairBuilder4(
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LDA, DoesntMatterWhatItDoesWith(State.N, State.Z),
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Not(ConcernsA),
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STA, DoesntMatterWhatItDoesWith(State.A)),
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operationPairBuilder4(
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LDX, DoesntMatterWhatItDoesWith(State.N, State.Z),
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Not(ConcernsX),
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STX, DoesntMatterWhatItDoesWith(State.X)),
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operationPairBuilder4(
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LDY, DoesntMatterWhatItDoesWith(State.N, State.Z),
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Not(ConcernsY),
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STY, DoesntMatterWhatItDoesWith(State.Y)),
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operationPairBuilder4(
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LAX, DoesntMatterWhatItDoesWith(State.N, State.Z),
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Not(ConcernsX) & Not(ConcernsA),
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STA, DoesntMatterWhatItDoesWith(State.A, State.X)),
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operationPairBuilder4(
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LAX, DoesntMatterWhatItDoesWith(State.N, State.Z),
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Not(ConcernsX) & Not(ConcernsA),
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STX, DoesntMatterWhatItDoesWith(State.A, State.X)),
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operationPairBuilder4(
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LAX, DoesntMatterWhatItDoesWith(State.N, State.Z),
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Not(ConcernsX) & Not(ConcernsA),
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SAX, DoesntMatterWhatItDoesWith(State.A, State.X)),
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)
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val PointlessStackStashing = new RuleBasedAssemblyOptimization("Pointless stack stashing",
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@ -762,27 +795,27 @@ object AlwaysGoodOptimizations {
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(HasOpcodeIn(Set(LDA, STA)) & HasAddrMode(Immediate) & MatchParameter(1)) ~
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(Linear & Not(ChangesA)).* ~
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(Linear & Not(ChangesA) & Not(HasOpcode(DISCARD_AF))).* ~
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(Elidable & HasOpcode(LDA) & HasAddrMode(Immediate) & MatchParameter(1)) ~~> (_.init),
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(HasOpcodeIn(Set(LDX, STX)) & HasAddrMode(Immediate) & MatchParameter(1)) ~
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(Linear & Not(ChangesX)).* ~
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(Linear & Not(ChangesX) & Not(HasOpcode(DISCARD_XF))).* ~
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(Elidable & HasOpcode(LDX) & HasAddrMode(Immediate) & MatchParameter(1)) ~~> (_.init),
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(HasOpcodeIn(Set(LDY, STY)) & HasAddrMode(Immediate) & MatchParameter(1)) ~
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(Linear & Not(ChangesY)).* ~
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(Linear & Not(ChangesY) & Not(HasOpcode(DISCARD_YF))).* ~
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(Elidable & HasOpcode(LDY) & HasAddrMode(Immediate) & MatchParameter(1)) ~~> (_.init),
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(HasOpcodeIn(Set(LDA, STA)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesA) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesA) & Not(HasOpcode(DISCARD_AF)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~~> (_.init),
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(HasOpcodeIn(Set(LDX, STX)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesX) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesX) & Not(HasOpcode(DISCARD_XF)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~~> (_.init),
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(HasOpcodeIn(Set(LDY, STY)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesY) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Linear & Not(ChangesY) & Not(HasOpcode(DISCARD_YF)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAt(0, 1)).* ~
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(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~~> (_.init),
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)
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@ -158,17 +158,17 @@ object LaterOptimizations {
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val DoubleLoadToTheSameRegister = new RuleBasedAssemblyOptimization("Double load to the same register",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LAX, Not(ChangesA) & Not(ChangesX)),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA)),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX)),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY)),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LAX, Not(ChangesA) & Not(ChangesX)),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA) & Not(HasOpcode(DISCARD_AF))),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY) & Not(HasOpcode(DISCARD_YF))),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LAX, Not(ChangesA) & Not(ChangesX) & Not(HasOpcode(DISCARD_AF)) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA) & Not(HasOpcode(DISCARD_AF))),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY) & Not(HasOpcode(DISCARD_YF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA) & Not(HasOpcode(DISCARD_AF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY) & Not(HasOpcode(DISCARD_YF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LAX, Not(ChangesA) & Not(ChangesX) & Not(HasOpcode(DISCARD_AF)) & Not(HasOpcode(DISCARD_XF))),
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InterleavedLoads(LDA, STA),
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InterleavedLoads(LDX, STX),
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InterleavedLoads(LDY, STY),
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