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6809: Improve flow analysis and add few more optimizations
This commit is contained in:
Karol Stasiak
parent
2e592a2331
commit
307ad90ecf
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@ -3,7 +3,7 @@
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#warn m6809_math module should be used only on 6809-like targets
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#endif
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noinline asm word __mul_u16u16u16(word register(x) x, word register(d) d) {
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noinline asm word __mul_u16u16u16(word register(x) x, word register(d) d) !preserves_y !preserves_u {
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pshs d,x
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exg d,x
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lda ,s
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@ -26,7 +26,7 @@ noinline asm word __mul_u16u16u16(word register(x) x, word register(d) d) {
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}
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// returns p/q: quotient in A, remainder in B
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noinline asm word __divmod_u8u8u8u8(word register(a) p, word register(b) q) {
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noinline asm word __divmod_u8u8u8u8(word register(a) p, word register(b) q) !preserves_x !preserves_y !preserves_u {
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pshs b,cc
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ldb #8
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stb ,-s
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@ -47,7 +47,7 @@ noinline asm word __divmod_u8u8u8u8(word register(a) p, word register(b) q) {
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}
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// returns p/q: quotient in X, remainder in D
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noinline asm word __divmod_u16u16u16u16(word register(x) p, word register(d) q) {
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noinline asm word __divmod_u16u16u16u16(word register(x) p, word register(d) q) !preserves_y !preserves_u {
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pshs x,d,cc
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ldb #16
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pshs b
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@ -254,9 +254,10 @@ case class MLine(opcode: MOpcode.Value, addrMode: MAddrMode, parameter: Constant
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case MUL => overlaps(D)
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case ABX => reg == X || overlaps(B)
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case NOP | SWI | SWI2 | SWI3 | SYNC => false
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case LDB | LDA | LDX | LDY | LDU => false
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case INC | DEC | ROL | ROR | ASL | ASR | LSR | CLR | COM | NEG | TST => false // variants for A and B handled before
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case op if Branching(op) => false
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case JMP => false
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case JMP | RTS => false
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case _ => true // TODO
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}
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}
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@ -3,7 +3,7 @@ package millfork.assembly.m6809.opt
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import millfork.assembly.AssemblyOptimization
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import millfork.assembly.m6809.MOpcode._
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import millfork.assembly.m6809.{Absolute, DAccumulatorIndexed, Immediate, InherentA, InherentB, LongRelative, MAddrMode, MLine, MState, PostIncremented, RegisterSet}
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import millfork.assembly.m6809.{Absolute, DAccumulatorIndexed, Immediate, Indexed, InherentA, InherentB, LongRelative, MAddrMode, MLine, MState, PostIncremented, RegisterSet}
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import millfork.env.{CompoundConstant, Constant, MathOperator}
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import millfork.node.M6809Register
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@ -253,6 +253,36 @@ object AlwaysGoodMOptimizations {
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)
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val SimplifiableAddressing = new RuleBasedAssemblyOptimization("Simplifiable addressing",
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needsFlowInfo = FlowInfoRequirement.ForwardFlow,
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(NotFixed & MatchX(0) & HasAddrMode(Indexed(M6809Register.X, indirect = false)) & Not(HasOpcodeIn(LEAX, LEAY, LEAS, LEAU))) ~~> { (code, ctx) =>
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val x = ctx.get[Constant](0)
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code.map(l => l.copy(addrMode = Absolute(indirect = false), parameter = (x + l.parameter).quickSimplify))
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},
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(NotFixed & MatchY(0) & HasAddrMode(Indexed(M6809Register.Y, indirect = false)) & Not(HasOpcodeIn(LEAX, LEAY, LEAS, LEAU))) ~~> { (code, ctx) =>
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val y = ctx.get[Constant](0)
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code.map(l => l.copy(addrMode = Absolute(indirect = false), parameter = (y + l.parameter).quickSimplify))
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},
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(NotFixed & MatchX(0) & HasAddrMode(Indexed(M6809Register.X, indirect = false)) & HasOpcodeIn(LEAX, LEAY, LEAS, LEAU)) ~~> { (code, ctx) =>
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val x = ctx.get[Constant](0)
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code.map(l => l.copy(opcode = l.opcode match {
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case LEAX => LDX
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case LEAY => LDY
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case LEAU => LDU
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case LEAS => LDS
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}, addrMode = Immediate, parameter = (x + l.parameter).quickSimplify))
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},
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(NotFixed & MatchY(0) & HasAddrMode(Indexed(M6809Register.X, indirect = false)) & HasOpcodeIn(LEAX, LEAY, LEAS, LEAU)) ~~> { (code, ctx) =>
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val y = ctx.get[Constant](0)
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code.map(l => l.copy(opcode = l.opcode match {
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case LEAX => LDX
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case LEAY => LDY
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case LEAU => LDU
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case LEAS => LDS
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}, addrMode = Immediate, parameter = (y + l.parameter).quickSimplify))
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},
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)
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val UnusedLabelRemoval = new RuleBasedAssemblyOptimization("Unused label removal",
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needsFlowInfo = FlowInfoRequirement.JustLabels,
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(Elidable & HasOpcode(LABEL) & HasCallerCount(0) & ParameterIsLocalLabel) ~~> (_ => Nil)
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@ -263,6 +293,7 @@ object AlwaysGoodMOptimizations {
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PointlessLoad,
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PointlessCompare,
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PointlessRegisterTransfers,
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SimplifiableAddressing,
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SimplifiableArithmetics,
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SimplifiableComparison,
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SimplifiableJumps,
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@ -35,6 +35,11 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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def nzB(i: Long): CpuStatus =
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this.copy(n = SingleStatus((i & 0x80) != 0), z = SingleStatus((i & 0xff) == 0))
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def nzB(i: Status[Int]): CpuStatus = i match {
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case SingleStatus(j) => this.copy(n = SingleStatus((j & 0x80) != 0), z = SingleStatus((j & 0xff) == 0))
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case _ => this.copy(n = AnyStatus, z = AnyStatus)
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}
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def nzW(i: Long): CpuStatus =
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this.copy(n = SingleStatus((i & 0x8000) != 0), z = SingleStatus((i & 0xffff) == 0))
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@ -44,6 +49,11 @@ case class CpuStatus(a: Status[Int] = UnknownStatus,
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case _ => this.nz
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}
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def nzW(i: Status[Int]): CpuStatus = i match {
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case SingleStatus(j) => this.copy(n = SingleStatus((j & 0x8000) != 0), z = SingleStatus((j & 0xffff) == 0))
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case _ => this.copy(n = AnyStatus, z = AnyStatus)
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}
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def ~(that: CpuStatus) = new CpuStatus(
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a = this.a ~ that.a,
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b = this.b ~ that.b,
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@ -2,10 +2,11 @@ package millfork.assembly.m6809.opt
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import millfork.CompilationFlag
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import millfork.assembly.OptimizationContext
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import millfork.assembly.m6809.{Immediate, MLine, MLine0}
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import millfork.assembly.m6809.{Absolute, Immediate, Inherent, InherentA, InherentB, MLine, MLine0, TwoRegisters}
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import millfork.assembly.opt.Status.SingleFalse
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import millfork.assembly.opt.{AnyStatus, FlowCache, SingleStatus, Status}
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import millfork.env._
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import millfork.node.M6809NiceFunctionProperty.{DoesntChangeA, DoesntChangeB, DoesntChangeU, DoesntChangeX, DoesntChangeY}
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import millfork.node.{M6809Register, NiceFunctionProperty}
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import scala.util.control.Breaks._
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@ -62,33 +63,108 @@ object ForwardFlowAnalysis {
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case _ => None
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}).fold(currentStatus)(_ ~ _)
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case MLine0(JSR, _, MemoryAddressConstant(th)) =>
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case MLine0(JSR, am, MemoryAddressConstant(th)) =>
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var prU = bpInU
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var prY = bpInY
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var prA = false
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var prB = false
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var prX = false
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(am, th) match {
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case (Absolute(false), fun: FunctionInMemory) =>
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val nfp = optimizationContext.niceFunctionProperties
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val fn = fun.name
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if (nfp(DoesntChangeX -> fn)) prX = true
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if (nfp(DoesntChangeY -> fn)) prY = true
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if (nfp(DoesntChangeU -> fn)) prU = true
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if (nfp(DoesntChangeA -> fn)) prA = true
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if (nfp(DoesntChangeB -> fn)) prB = true
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case _ =>
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}
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currentStatus = initialStatus.copy(
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memStack = currentStatus.memStack,
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u = if (bpInU) currentStatus.u else AnyStatus,
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y = if (bpInY) currentStatus.y else AnyStatus
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u = if (prU) currentStatus.u else AnyStatus,
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x = if (prX) currentStatus.x else AnyStatus,
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y = if (prY) currentStatus.y else AnyStatus,
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a = if (prA) currentStatus.a else AnyStatus,
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b = if (prB) currentStatus.b else AnyStatus
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)
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case MLine0(JSR | BYTE, _, _) =>
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currentStatus = initialStatus
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case MLine0(NOP, _, _) =>
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()
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case MLine0(op, Immediate, constant) if ForwardFlowAnalysisForImmediate.hasDefinition(op) =>
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ForwardFlowAnalysisForImmediate.get(op)(constant, currentStatus)
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case MLine0(op, Inherent, _) if ForwardFlowAnalysisForInherent.hasDefinition(op) =>
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ForwardFlowAnalysisForInherent.get(op)(currentStatus)
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case MLine0(op, InherentA, _) if ForwardFlowAnalysisForInherentA.hasDefinition(op) =>
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ForwardFlowAnalysisForInherentA.get(op)(currentStatus)
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case MLine0(op, InherentB, _) if ForwardFlowAnalysisForInherentB.hasDefinition(op) =>
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ForwardFlowAnalysisForInherentB.get(op)(currentStatus)
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case MLine0(LDA, Immediate, NumericConstant(n, _)) =>
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currentStatus = currentStatus.copy(a = SingleStatus(n.toInt & 0xff), v = SingleFalse).nzB(n)
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case MLine0(LDB, Immediate, NumericConstant(n, _)) =>
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currentStatus = currentStatus.copy(b = SingleStatus(n.toInt & 0xff), v = SingleFalse).nzB(n)
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case MLine0(LDD, Immediate, NumericConstant(n, _)) =>
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currentStatus = currentStatus.copy(
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a = SingleStatus(n.toInt.>>(8) & 0xff),
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b = SingleStatus(n.toInt & 0xff),
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v = SingleFalse
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).nzW(n)
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case MLine0(LDX, Immediate, c) =>
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currentStatus = currentStatus.copy(x = SingleStatus(c), v = SingleFalse).nzW(c)
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case MLine0(LDY, Immediate, c) =>
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currentStatus = currentStatus.copy(y = SingleStatus(c), v = SingleFalse).nzW(c)
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case MLine0(LDA, _, _) =>
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currentStatus = currentStatus.copy(a = AnyStatus, n = AnyStatus, z = AnyStatus, v = SingleFalse)
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case MLine0(LDB, _, _) =>
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currentStatus = currentStatus.copy(b = AnyStatus, n = AnyStatus, z = AnyStatus, v = SingleFalse)
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case MLine0(LDD, _, _) =>
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currentStatus = currentStatus.copy(a = AnyStatus, b = AnyStatus, n = AnyStatus, z = AnyStatus, v = SingleFalse)
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case MLine0(LDX, _, _) =>
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currentStatus = currentStatus.copy(x = AnyStatus, n = AnyStatus, z = AnyStatus, v = SingleFalse)
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case MLine0(LDY, _, _) =>
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currentStatus = currentStatus.copy(y = AnyStatus, n = AnyStatus, z = AnyStatus, v = SingleFalse)
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case MLine0(STA | STB | STD | STX | STU | STY | STS, _, _) =>
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// don't change
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case MLine0(TFR, TwoRegisters(source, target), _) =>
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import M6809Register._
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(source, target) match {
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case (A, B) => currentStatus = currentStatus.copy(b = currentStatus.a)
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case (B, A) => currentStatus = currentStatus.copy(a = currentStatus.b)
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case (CC, A) => currentStatus = currentStatus.copy(a = AnyStatus)
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case (CC, B) => currentStatus = currentStatus.copy(b = AnyStatus)
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case (A, CC) | (B, CC) => currentStatus = currentStatus.copy(c = AnyStatus, z = AnyStatus, n = AnyStatus, v = AnyStatus)
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case (S, D) => currentStatus = currentStatus.copy(a = AnyStatus, b = AnyStatus)
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case (S, X) => currentStatus = currentStatus.copy(x = AnyStatus)
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case (S, Y) => currentStatus = currentStatus.copy(y = AnyStatus)
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case (S, U) => currentStatus = currentStatus.copy(u = AnyStatus)
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case (D, X) => currentStatus = currentStatus.copy(x = currentStatus.d.map(n => NumericConstant(n, 2)))
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case (D, Y) => currentStatus = currentStatus.copy(y = currentStatus.d.map(n => NumericConstant(n, 2)))
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case (D, U) => currentStatus = currentStatus.copy(u = currentStatus.d.map(n => NumericConstant(n, 2)))
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case (X, Y) => currentStatus = currentStatus.copy(y = currentStatus.x)
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case (X, U) => currentStatus = currentStatus.copy(u = currentStatus.x)
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case (Y, X) => currentStatus = currentStatus.copy(x = currentStatus.y)
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case (Y, U) => currentStatus = currentStatus.copy(u = currentStatus.y)
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case (U, X) => currentStatus = currentStatus.copy(x = currentStatus.u)
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case (U, Y) => currentStatus = currentStatus.copy(y = currentStatus.u)
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case (X, D) =>
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val (h, l) = currentStatus.x.toHiLo
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currentStatus = currentStatus.copy(a = h, b = l)
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case (Y, D) =>
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val (h, l) = currentStatus.y.toHiLo
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currentStatus = currentStatus.copy(a = h, b = l)
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case (U, D) =>
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val (h, l) = currentStatus.u.toHiLo
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currentStatus = currentStatus.copy(a = h, b = l)
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case _ => currentStatus = initialStatus
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}
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case MLine0(EXG, TwoRegisters(source, target), _) =>
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import M6809Register._
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(source, target) match {
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case (A, B) | (B, A) => currentStatus = currentStatus.copy(a = currentStatus.b, b = currentStatus.a)
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case (A, CC) | (CC, A) => currentStatus = currentStatus.copy(a = AnyStatus, c = AnyStatus, v = AnyStatus, n = AnyStatus, z = AnyStatus)
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case (B, CC) | (CC, B) => currentStatus = currentStatus.copy(b = AnyStatus, c = AnyStatus, v = AnyStatus, n = AnyStatus, z = AnyStatus)
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case (X, Y) | (Y, X) => currentStatus = currentStatus.copy(y = currentStatus.x, x = currentStatus.y)
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case (U, Y) | (Y, U) => currentStatus = currentStatus.copy(y = currentStatus.u, u = currentStatus.y)
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case (X, U) | (U, X) => currentStatus = currentStatus.copy(u = currentStatus.x, x = currentStatus.u)
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case (X, D) | (D, X) =>
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val (h, l) = currentStatus.x.toHiLo
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currentStatus = currentStatus.copy(a = h, b = l, x = currentStatus.d.map(n => NumericConstant(n, 2)))
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case (Y, D) | (D, Y) =>
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val (h, l) = currentStatus.y.toHiLo
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currentStatus = currentStatus.copy(a = h, b = l, y = currentStatus.d.map(n => NumericConstant(n, 2)))
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case (U, D) | (D, U) =>
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val (h, l) = currentStatus.u.toHiLo
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currentStatus = currentStatus.copy(a = h, b = l, u = currentStatus.d.map(n => NumericConstant(n, 2)))
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case _ => currentStatus = initialStatus
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}
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case MLine0(opcode, addrMode, _) =>
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// TODO
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@ -0,0 +1,80 @@
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package millfork.assembly.m6809.opt
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import millfork.assembly.m6809.MOpcode
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import millfork.assembly.m6809.MOpcode._
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import millfork.assembly.opt.{AnyStatus, SingleStatus, Status}
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import millfork.assembly.opt.Status.SingleFalse
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import millfork.env.Constant
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/**
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* @author Karol Stasiak
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*/
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object ForwardFlowAnalysisForImmediate {
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private val map: Map[MOpcode.Value, (Constant, CpuStatus) => CpuStatus] = Map(
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LDX -> {(c, currentStatus) =>
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currentStatus.copy(x = SingleStatus(c), v = SingleFalse).nzW(c)
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},
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LDY -> {(c, currentStatus) =>
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currentStatus.copy(y = SingleStatus(c), v = SingleFalse).nzW(c)
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},
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LDU -> {(c, currentStatus) =>
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currentStatus.copy(u = SingleStatus(c), v = SingleFalse).nzW(c)
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},
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LDA -> {(c, currentStatus) =>
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val value = Status.fromByte(c)
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currentStatus.copy(a = value, v = SingleFalse).nzB(value)
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},
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LDB -> {(c, currentStatus) =>
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val value = Status.fromByte(c)
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currentStatus.copy(a = value, v = SingleFalse).nzB(value)
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},
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LDD -> {(c, currentStatus) =>
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val value = Status.fromByte(c)
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currentStatus.copy(a = value.hi, b = value.lo, v = SingleFalse).nzW(value)
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},
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ORA -> { (c, currentStatus) =>
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val newValue = (currentStatus.a <*> Status.fromByte(c)) { (x, y) => (x | y) & 0xff }
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currentStatus.copy(a = newValue, v = SingleFalse).nzB(newValue)
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},
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ORB -> { (c, currentStatus) =>
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val newValue = (currentStatus.b <*> Status.fromByte(c)) { (x, y) => (x | y) & 0xff }
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currentStatus.copy(b = newValue, v = SingleFalse).nzB(newValue)
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},
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EORA -> { (c, currentStatus) =>
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val newValue = (currentStatus.a <*> Status.fromByte(c)) { (x, y) => (x ^ y) & 0xff }
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currentStatus.copy(a = newValue, v = SingleFalse).nzB(newValue)
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},
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EORB -> { (c, currentStatus) =>
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val newValue = (currentStatus.b <*> Status.fromByte(c)) { (x, y) => (x ^ y) & 0xff }
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currentStatus.copy(b = newValue, v = SingleFalse).nzB(newValue)
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},
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ANDA -> { (c, currentStatus) =>
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val newValue = (currentStatus.a <*> Status.fromByte(c)) { (x, y) => (x & y) & 0xff }
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currentStatus.copy(a = newValue, v = SingleFalse).nzB(newValue)
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},
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ANDB -> { (c, currentStatus) =>
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val newValue = (currentStatus.b <*> Status.fromByte(c)) { (x, y) => (x & y) & 0xff }
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currentStatus.copy(b = newValue, v = SingleFalse).nzB(newValue)
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},
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ADDA -> { (c, currentStatus) =>
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val (newValue, newCarry) = currentStatus.a.adc(Status.fromByte(c), SingleFalse)
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currentStatus.copy(a = newValue, v = AnyStatus, c = newCarry).nzB(newValue)
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},
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ADDB -> { (c, currentStatus) =>
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val (newValue, newCarry) = currentStatus.b.adc(Status.fromByte(c), SingleFalse)
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currentStatus.copy(b = newValue, v = AnyStatus, c = newCarry).nzB(newValue)
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},
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ADCA -> { (c, currentStatus) =>
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val (newValue, newCarry) = currentStatus.a.adc(Status.fromByte(c), currentStatus.c)
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currentStatus.copy(a = newValue, v = AnyStatus, c = newCarry).nzB(newValue)
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},
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ADCB -> { (c, currentStatus) =>
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val (newValue, newCarry) = currentStatus.b.adc(Status.fromByte(c), currentStatus.c)
|
||||
currentStatus.copy(b = newValue, v = AnyStatus, c = newCarry).nzB(newValue)
|
||||
},
|
||||
)
|
||||
|
||||
def hasDefinition(opcode: MOpcode.Value): Boolean = map.contains(opcode)
|
||||
|
||||
def get(opcode: MOpcode.Value): (Constant, CpuStatus) => CpuStatus = map(opcode)
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
package millfork.assembly.m6809.opt
|
||||
|
||||
import millfork.assembly.m6809.MOpcode
|
||||
import millfork.assembly.m6809.MOpcode._
|
||||
import millfork.assembly.opt.Status.SingleFalse
|
||||
import millfork.assembly.opt.{AnyStatus, SingleStatus, Status}
|
||||
import millfork.env.Constant
|
||||
|
||||
/**
|
||||
* @author Karol Stasiak
|
||||
*/
|
||||
object ForwardFlowAnalysisForInherent {
|
||||
private val map: Map[MOpcode.Value, CpuStatus => CpuStatus] = Map(
|
||||
NOP -> identity,
|
||||
MUL -> { currentStatus =>
|
||||
val newD = (currentStatus.a <*> currentStatus.b) { (a, b) => ((a & 0xff) * (b & 0xff)) & 0xff }
|
||||
currentStatus.copy(c = AnyStatus, z = AnyStatus, a = newD.hi, b = newD.hi)
|
||||
},
|
||||
SEX -> { currentStatus =>
|
||||
val newA = currentStatus.b.map{ n => if (n.&(0x80) == 0) 0 else 0xff }
|
||||
currentStatus.copy(v = Status.SingleFalse, n = AnyStatus, z = AnyStatus, a = newA)
|
||||
},
|
||||
)
|
||||
|
||||
def hasDefinition(opcode: MOpcode.Value): Boolean = map.contains(opcode)
|
||||
|
||||
def get(opcode: MOpcode.Value): CpuStatus => CpuStatus = map(opcode)
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
package millfork.assembly.m6809.opt
|
||||
|
||||
import millfork.assembly.m6809.MOpcode
|
||||
import millfork.assembly.m6809.MOpcode._
|
||||
import millfork.assembly.opt.{AnyStatus, SingleStatus, Status}
|
||||
|
||||
/**
|
||||
* @author Karol Stasiak
|
||||
*/
|
||||
object ForwardFlowAnalysisForInherentA {
|
||||
private val map: Map[MOpcode.Value, CpuStatus => CpuStatus] = Map(
|
||||
ASL -> { currentStatus =>
|
||||
val newValue = currentStatus.a.map(n => n.<<(1).&(0xff))
|
||||
currentStatus.copy(a = newValue, c = currentStatus.a.bit7, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
LSR -> { currentStatus =>
|
||||
val newValue = currentStatus.a.map(n => n.>>(1).&(0x7f))
|
||||
currentStatus.copy(a = newValue, c = currentStatus.a.bit0, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
CLR -> { currentStatus =>
|
||||
currentStatus.copy(a = Status.SingleZero, c = Status.SingleFalse, v = Status.SingleFalse, n = Status.SingleFalse, z = Status.SingleFalse)
|
||||
},
|
||||
COM -> { currentStatus =>
|
||||
val newValue = currentStatus.a.map(n => n.^(0xff).&(0xff))
|
||||
currentStatus.copy(a = newValue, c = Status.SingleTrue, v = Status.SingleFalse).nzB(newValue)
|
||||
},
|
||||
DEC -> { currentStatus =>
|
||||
val newValue = currentStatus.a.map(n => n.+(1).&(0xff))
|
||||
currentStatus.copy(a = newValue, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
INC -> { currentStatus =>
|
||||
val newValue = currentStatus.a.map(n => n.-(1).&(0xff))
|
||||
currentStatus.copy(a = newValue, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
NEG -> { currentStatus =>
|
||||
val newValue = currentStatus.a.map(n => (-n).&(0xff))
|
||||
currentStatus.copy(a = newValue, c = AnyStatus, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
TST -> { currentStatus =>
|
||||
currentStatus.copy(v = Status.SingleFalse).nzB(currentStatus.a)
|
||||
},
|
||||
)
|
||||
|
||||
def hasDefinition(opcode: MOpcode.Value): Boolean = map.contains(opcode)
|
||||
|
||||
def get(opcode: MOpcode.Value): CpuStatus => CpuStatus = map(opcode)
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
package millfork.assembly.m6809.opt
|
||||
|
||||
import millfork.assembly.m6809.MOpcode
|
||||
import millfork.assembly.m6809.MOpcode._
|
||||
import millfork.assembly.opt.{AnyStatus, Status}
|
||||
|
||||
/**
|
||||
* @author Karol Stasiak
|
||||
*/
|
||||
object ForwardFlowAnalysisForInherentB {
|
||||
private val map: Map[MOpcode.Value, CpuStatus => CpuStatus] = Map(
|
||||
ASL -> { currentStatus =>
|
||||
val newValue = currentStatus.b.map(n => n.<<(1).&(0xff))
|
||||
currentStatus.copy(b = newValue, c = currentStatus.b.bit7, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
LSR -> { currentStatus =>
|
||||
val newValue = currentStatus.b.map(n => n.>>(1).&(0x7f))
|
||||
currentStatus.copy(b = newValue, c = currentStatus.b.bit0, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
CLR -> { currentStatus =>
|
||||
currentStatus.copy(b = Status.SingleZero, c = Status.SingleFalse, v = Status.SingleFalse, n = Status.SingleFalse, z = Status.SingleFalse)
|
||||
},
|
||||
COM -> { currentStatus =>
|
||||
val newValue = currentStatus.b.map(n => n.^(0xff).&(0xff))
|
||||
currentStatus.copy(b = newValue, c = Status.SingleTrue, v = Status.SingleFalse).nzB(newValue)
|
||||
},
|
||||
DEC -> { currentStatus =>
|
||||
val newValue = currentStatus.b.map(n => n.+(1).&(0xff))
|
||||
currentStatus.copy(b = newValue, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
INC -> { currentStatus =>
|
||||
val newValue = currentStatus.b.map(n => n.-(1).&(0xff))
|
||||
currentStatus.copy(b = newValue, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
NEG -> { currentStatus =>
|
||||
val newValue = currentStatus.b.map(n => (-n).&(0xff))
|
||||
currentStatus.copy(b = newValue, c = AnyStatus, v = AnyStatus).nzB(newValue)
|
||||
},
|
||||
TST -> { currentStatus =>
|
||||
currentStatus.copy(v = Status.SingleFalse).nzB(currentStatus.b)
|
||||
},
|
||||
)
|
||||
|
||||
def hasDefinition(opcode: MOpcode.Value): Boolean = map.contains(opcode)
|
||||
|
||||
def get(opcode: MOpcode.Value): CpuStatus => CpuStatus = map(opcode)
|
||||
}
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
package millfork.assembly.m6809.opt
|
||||
|
||||
import jdk.jfr.BooleanFlag
|
||||
import millfork.CompilationFlag
|
||||
import millfork.assembly._
|
||||
import millfork.assembly.m6809.{Absolute, MLine, MLine0, MOpcode, MState}
|
||||
import millfork.assembly.opt.FlowCache
|
||||
|
|
@ -82,6 +83,7 @@ object ReverseFlowAnalyzer {
|
|||
val readsB: Set[String] = Set("call")
|
||||
val readsX: Set[String] = Set("call")
|
||||
val readsY: Set[String] = Set("")
|
||||
val preservesX: Set[String] = Set("__divmod_u8u8u8u8")
|
||||
|
||||
val cache = new FlowCache[MLine, CpuImportance]("m6809 reverse")
|
||||
private val importanceBeforeJsr: CpuImportance = CpuImportance(
|
||||
|
|
@ -97,7 +99,7 @@ object ReverseFlowAnalyzer {
|
|||
hf = Unimportant)
|
||||
private val finalImportance: CpuImportance = CpuImportance(
|
||||
a = Important, b = Important,
|
||||
x = Important, y = Important, u = Important,
|
||||
x = Important, y = Important, u = Important, // TODO: correctly check which registers are important given the function and the compilation options
|
||||
cf = Unimportant, vf = Unimportant, hf = Unimportant, zf = Unimportant, nf = Unimportant)
|
||||
|
||||
//noinspection RedundantNewCaseClass
|
||||
|
|
@ -109,11 +111,23 @@ object ReverseFlowAnalyzer {
|
|||
|
||||
var changed = true
|
||||
changed = true
|
||||
val actualFinalImportance = f.returnType match {
|
||||
case FlagBooleanType(_, _, _) => finalImportance.copy(cf = Important, zf = Important, nf = Important, vf = Important)
|
||||
case t if t.size == 1 => finalImportance.copy(a = Unimportant)
|
||||
case t if t.size == 0 => finalImportance.copy(a = Unimportant, b = Unimportant)
|
||||
case _ => finalImportance
|
||||
val actualFinalImportance = {
|
||||
var tmp = f.returnType match {
|
||||
case FlagBooleanType(_, _, _) => finalImportance.copy(cf = Important, zf = Important, nf = Important, vf = Important)
|
||||
case t if t.size == 1 => finalImportance.copy(a = Unimportant)
|
||||
case t if t.size == 0 => finalImportance.copy(a = Unimportant, b = Unimportant)
|
||||
case _ => finalImportance
|
||||
}
|
||||
if (!f.inAssembly) {
|
||||
tmp = tmp.copy(x = Unimportant)
|
||||
if (!optimizationContext.options.flag(CompilationFlag.UseUForStack)) {
|
||||
tmp = tmp.copy(u = Unimportant)
|
||||
}
|
||||
if (!optimizationContext.options.flag(CompilationFlag.UseYForStack)) {
|
||||
tmp = tmp.copy(y = Unimportant)
|
||||
}
|
||||
}
|
||||
tmp
|
||||
}
|
||||
while (changed) {
|
||||
changed = false
|
||||
|
|
@ -179,6 +193,7 @@ object ReverseFlowAnalyzer {
|
|||
if (readsB(fun.name)) result = result.copy(b = Important)
|
||||
if (readsX(fun.name)) result = result.copy(x = Important)
|
||||
if (readsY(fun.name)) result = result.copy(y = Important)
|
||||
if (preservesX(fun.name)) result = result.copy(x = currentImportance.x)
|
||||
currentImportance = result.copy(
|
||||
a = if (niceFunctionProperties(DoesntChangeA -> fun.name)) currentImportance.a ~ result.a else result.a,
|
||||
b = if (niceFunctionProperties(DoesntChangeB -> fun.name)) currentImportance.b ~ result.b else result.b,
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
package millfork.assembly.opt
|
||||
|
||||
import millfork.assembly.mos.opt.SourceOfNZ
|
||||
import millfork.env.{Constant, NumericConstant}
|
||||
|
||||
/**
|
||||
* @author Karol Stasiak
|
||||
|
|
@ -78,6 +79,16 @@ object Status {
|
|||
val SingleZero: Status[Int] = SingleStatus(0)
|
||||
val SingleFF: Status[Int] = SingleStatus(0xff)
|
||||
|
||||
def fromByte(c: Constant): Status[Int] = c.loByte match {
|
||||
case NumericConstant(n, _) => SingleStatus(n.toInt & 0xff)
|
||||
case _ => AnyStatus
|
||||
}
|
||||
|
||||
def fromWord(c: Constant): Status[Int] = c match {
|
||||
case NumericConstant(n, _) => SingleStatus(n.toInt & 0xffff)
|
||||
case _ => AnyStatus
|
||||
}
|
||||
|
||||
@inline
|
||||
private def wrapBool(b: Boolean): Status[Boolean] = if (b) SingleTrue else SingleFalse
|
||||
|
||||
|
|
@ -109,6 +120,13 @@ object Status {
|
|||
case x => x
|
||||
}
|
||||
}
|
||||
|
||||
implicit class ConstantStatusOps(val inner: Status[Constant]) extends AnyVal {
|
||||
def toHiLo: (Status[Int], Status[Int]) = inner match {
|
||||
case SingleStatus(NumericConstant(n, _)) => SingleStatus(n.toInt.>>(8).&(0xff)) -> SingleStatus(n.toInt.&(0xff))
|
||||
case _ => AnyStatus -> AnyStatus
|
||||
}
|
||||
}
|
||||
implicit class SourceOfNZStatusOps(val inner: Status[SourceOfNZ]) extends AnyVal {
|
||||
def isFromA: Boolean = inner match {
|
||||
case SingleStatus(v) => v.a
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user