From 35f06d548694100692df3271a9bfea227927b2d9 Mon Sep 17 00:00:00 2001
From: Karol Stasiak <karol.m.stasiak@gmail.com>
Date: Sat, 3 Mar 2018 14:31:06 +0100
Subject: [PATCH] Optimizer shouldn't remove LDA's before TSR and TRB

---
 src/main/scala/millfork/assembly/AssemblyLine.scala    |  5 +++++
 src/main/scala/millfork/assembly/Opcode.scala          | 10 +++++-----
 .../millfork/assembly/opt/CmosOptimizations.scala      |  2 +-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/millfork/assembly/AssemblyLine.scala b/src/main/scala/millfork/assembly/AssemblyLine.scala
index f11ab274..d6fdb9a7 100644
--- a/src/main/scala/millfork/assembly/AssemblyLine.scala
+++ b/src/main/scala/millfork/assembly/AssemblyLine.scala
@@ -13,6 +13,8 @@ object OpcodeClasses {
     ADC_W, AND_W, BIT_W, CMP_W, EOR_W, ORA_W, PHA_W, SBC_W, STA_W,
     TAX, TAY,
     SAX, SBX, ANC, DCP, ISC, RRA, RLA, SRE, SLO, LXA, XAA, AHX, TAS,
+    TSB, TRB,
+    TSB_W, TRB_W,
     TAZ, TAB,
     HuSAX, SAY, TAM,
     TCD, TCS, XBA,
@@ -24,6 +26,7 @@ object OpcodeClasses {
   val ReadsAHAlways = Set(
     ADC_W, AND_W, BIT_W, CMP_W, EOR_W, ORA_W, PHA_W, SBC_W, STA_W,
     TCD, TCS, XBA,
+    TSB_W, TRB_W,
   )
   val ReadsAHIfImplied = Set(
     DEC_W, INC_W, ROL_W, ROR_W, ASL_W, LSR_W,
@@ -113,6 +116,8 @@ object OpcodeClasses {
   val ChangesIZ = Set(
     DEZ, INZ, TAZ, LDZ,
   )
+  val ChangesDirectPageRegister = Set(XCE, PLD, TCD)
+  val ChangesDataBankRegister = Set(XCE, PLB, MVN, MVP)
   val ChangesS = Set(
     PHA, PLA,
     PHA_W, PLA_W,
diff --git a/src/main/scala/millfork/assembly/Opcode.scala b/src/main/scala/millfork/assembly/Opcode.scala
index 7b79cd48..4d8fa06c 100644
--- a/src/main/scala/millfork/assembly/Opcode.scala
+++ b/src/main/scala/millfork/assembly/Opcode.scala
@@ -82,14 +82,14 @@ object Opcode extends Enumeration {
   // 65CE02:
   CPZ, LDZ, DEZ, INZ,
   PHW,
-  // DEW, INW, ASW, ROW, // aliases for DEC_W, INC_W, ASL_W, ROL_W (?)
+  // DEW, INW, ASW, ROW, // aliases for DEC_W, INC_W, ASL_W, ROR_W (?)
   NEG, ASR,
   TAZ, TZA, PHZ, PLZ,
   TSY, TYS,
   TAB, TBA,
-  // CLE, SEE,
+  CLE, SEE, // no idea what these do
   BSR,
-  // MAP,
+  MAP, // also called AUG
 
   //HuC6280:
   CLA, CLX, CLY,
@@ -99,13 +99,13 @@ object Opcode extends Enumeration {
   // ST0, ST1, ST2,
   // BSR, // the same as on 65CE02
   TAM, TMA,
-  // TAI, TIA, TDD, TIN, TII, // memcpy instructions
+  TAI, TIA, TDD, TIN, TII, // memcpy instructions
   TST,
 
   //65816:
   BRL,
   COP,
-  // MVN, MVP,
+  MVN, MVP, // memcpy instructions
   PEA, PEI, PER,
   PHB, PHD, PHK, PLB, PLD, // there's no PLK for the same reason Intel removed POP CS from 80186
   REP, SEP,
diff --git a/src/main/scala/millfork/assembly/opt/CmosOptimizations.scala b/src/main/scala/millfork/assembly/opt/CmosOptimizations.scala
index 1b40030b..3fdbdda6 100644
--- a/src/main/scala/millfork/assembly/opt/CmosOptimizations.scala
+++ b/src/main/scala/millfork/assembly/opt/CmosOptimizations.scala
@@ -37,7 +37,7 @@ object CmosOptimizations {
       (Elidable & HasOpcode(AND) & MatchImmediate(1)) ~
       (Elidable & HasOpcode(STA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.A, State.Z, State.N)) ~~> { code =>
       List(
-        code(1).copy(opcode = Opcode.LDA, parameter = CompoundConstant(MathOperator.Exor, NumericConstant(255, 1), code(1).parameter)),
+        code(1).copy(opcode = Opcode.LDA, parameter = CompoundConstant(MathOperator.Exor, NumericConstant(255, 1), code(1).parameter).quickSimplify),
         code.head.copy(opcode = TRB))
     },
   )