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Optimizer shouldn't remove LDA's before TSR and TRB

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This commit is contained in:
Karol Stasiak 2018-03-03 14:31:06 +01:00
parent 6ed5d51260
commit 35f06d5486
3 changed files with 11 additions and 6 deletions
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5
src/main/scala/millfork/assembly/AssemblyLine.scala
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@ -13,6 +13,8 @@ object OpcodeClasses {
ADC_W, AND_W, BIT_W, CMP_W, EOR_W, ORA_W, PHA_W, SBC_W, STA_W, ADC_W, AND_W, BIT_W, CMP_W, EOR_W, ORA_W, PHA_W, SBC_W, STA_W,
TAX, TAY, TAX, TAY,
SAX, SBX, ANC, DCP, ISC, RRA, RLA, SRE, SLO, LXA, XAA, AHX, TAS, SAX, SBX, ANC, DCP, ISC, RRA, RLA, SRE, SLO, LXA, XAA, AHX, TAS,
TSB, TRB,
TSB_W, TRB_W,
TAZ, TAB, TAZ, TAB,
HuSAX, SAY, TAM, HuSAX, SAY, TAM,
TCD, TCS, XBA, TCD, TCS, XBA,
@ -24,6 +26,7 @@ object OpcodeClasses {
val ReadsAHAlways = Set( val ReadsAHAlways = Set(
ADC_W, AND_W, BIT_W, CMP_W, EOR_W, ORA_W, PHA_W, SBC_W, STA_W, ADC_W, AND_W, BIT_W, CMP_W, EOR_W, ORA_W, PHA_W, SBC_W, STA_W,
TCD, TCS, XBA, TCD, TCS, XBA,
TSB_W, TRB_W,
) )
val ReadsAHIfImplied = Set( val ReadsAHIfImplied = Set(
DEC_W, INC_W, ROL_W, ROR_W, ASL_W, LSR_W, DEC_W, INC_W, ROL_W, ROR_W, ASL_W, LSR_W,
@ -113,6 +116,8 @@ object OpcodeClasses {
val ChangesIZ = Set( val ChangesIZ = Set(
DEZ, INZ, TAZ, LDZ, DEZ, INZ, TAZ, LDZ,
) )
val ChangesDirectPageRegister = Set(XCE, PLD, TCD)
val ChangesDataBankRegister = Set(XCE, PLB, MVN, MVP)
val ChangesS = Set( val ChangesS = Set(
PHA, PLA, PHA, PLA,
PHA_W, PLA_W, PHA_W, PLA_W,

10
src/main/scala/millfork/assembly/Opcode.scala
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@ -82,14 +82,14 @@ object Opcode extends Enumeration {
// 65CE02: // 65CE02:
CPZ, LDZ, DEZ, INZ, CPZ, LDZ, DEZ, INZ,
PHW, PHW,
// DEW, INW, ASW, ROW, // aliases for DEC_W, INC_W, ASL_W, ROL_W (?) // DEW, INW, ASW, ROW, // aliases for DEC_W, INC_W, ASL_W, ROR_W (?)
NEG, ASR, NEG, ASR,
TAZ, TZA, PHZ, PLZ, TAZ, TZA, PHZ, PLZ,
TSY, TYS, TSY, TYS,
TAB, TBA, TAB, TBA,
// CLE, SEE, CLE, SEE, // no idea what these do
BSR, BSR,
// MAP, MAP, // also called AUG
//HuC6280: //HuC6280:
CLA, CLX, CLY, CLA, CLX, CLY,
@ -99,13 +99,13 @@ object Opcode extends Enumeration {
// ST0, ST1, ST2, // ST0, ST1, ST2,
// BSR, // the same as on 65CE02 // BSR, // the same as on 65CE02
TAM, TMA, TAM, TMA,
// TAI, TIA, TDD, TIN, TII, // memcpy instructions TAI, TIA, TDD, TIN, TII, // memcpy instructions
TST, TST,
//65816: //65816:
BRL, BRL,
COP, COP,
// MVN, MVP, MVN, MVP, // memcpy instructions
PEA, PEI, PER, PEA, PEI, PER,
PHB, PHD, PHK, PLB, PLD, // there's no PLK for the same reason Intel removed POP CS from 80186 PHB, PHD, PHK, PLB, PLD, // there's no PLK for the same reason Intel removed POP CS from 80186
REP, SEP, REP, SEP,

2
src/main/scala/millfork/assembly/opt/CmosOptimizations.scala
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@ -37,7 +37,7 @@ object CmosOptimizations {
(Elidable & HasOpcode(AND) & MatchImmediate(1)) ~ (Elidable & HasOpcode(AND) & MatchImmediate(1)) ~
(Elidable & HasOpcode(STA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.A, State.Z, State.N)) ~~> { code => (Elidable & HasOpcode(STA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.A, State.Z, State.N)) ~~> { code =>
List( List(
code(1).copy(opcode = Opcode.LDA, parameter = CompoundConstant(MathOperator.Exor, NumericConstant(255, 1), code(1).parameter)), code(1).copy(opcode = Opcode.LDA, parameter = CompoundConstant(MathOperator.Exor, NumericConstant(255, 1), code(1).parameter).quickSimplify),
code.head.copy(opcode = TRB)) code.head.copy(opcode = TRB))
}, },
) )