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Emit LD (m),BC and similar instructions

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This commit is contained in:
Karol Stasiak 2018-07-16 23:01:04 +02:00
parent 704ae17d30
commit 39dfe13a3f
1 changed files with 10 additions and 0 deletions
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10
src/main/scala/millfork/output/Z80Assembler.scala
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@ -101,6 +101,16 @@ class Z80Assembler(program: Program,
writeByte(bank, index, 0x22)
writeWord(bank, index + 1, param)
index + 3
case ZLine(LD_16, TwoRegisters(reg@(ZRegister.BC | ZRegister.DE | ZRegister.SP), ZRegister.MEM_ABS_16), param, _) =>
writeByte(bank, index, 0xed)
writeByte(bank, index+1, 0x4b + 0x10 * internalRegisterIndex(reg))
writeWord(bank, index + 2, param)
index + 4
case ZLine(LD_16, TwoRegisters(ZRegister.MEM_ABS_16, reg@(ZRegister.BC | ZRegister.DE | ZRegister.SP)), param, _) =>
writeByte(bank, index, 0xed)
writeByte(bank, index+1, 0x43 + 0x10 * internalRegisterIndex(reg))
writeWord(bank, index + 2, param)
index + 4
case ZLine(LD_16, TwoRegisters(ZRegister.SP, ZRegister.HL), _, _) =>
writeByte(bank, index, 0xF9)
index + 1