diff --git a/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala b/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
index 5eeca983..1d34cd13 100644
--- a/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
+++ b/src/main/scala/millfork/assembly/z80/opt/AlwaysGoodI80Optimizations.scala
@@ -374,6 +374,14 @@ object AlwaysGoodI80Optimizations {
       Nil
     },
 
+    (Elidable & HasOpcode(ADD) & Has8BitImmediate(1) & DoesntMatterWhatItDoesWithFlagsOtherThanSZ) ~~> { _ =>
+      List(ZLine.register(INC, A))
+    },
+
+    (Elidable & HasOpcode(SUB) & Has8BitImmediate(1) & DoesntMatterWhatItDoesWithFlagsOtherThanSZ) ~~> { _ =>
+      List(ZLine.register(DEC, A))
+    },
+
     (Elidable & HasOpcode(ADD_16) & HasRegisters(TwoRegisters(ZRegister.HL, ZRegister.BC)) & HasRegister(ZRegister.BC, 1) & DoesntMatterWhatItDoesWithFlags) ~~> { (code, ctx) =>
       List(ZLine.register(ZOpcode.INC_16, ZRegister.HL))
     },
diff --git a/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala b/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala
index 25525747..1f86216b 100644
--- a/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala
+++ b/src/main/scala/millfork/assembly/z80/opt/LaterI80Optimizations.scala
@@ -1,7 +1,7 @@
 package millfork.assembly.z80.opt
 
 import millfork.assembly.AssemblyOptimization
-import millfork.assembly.z80.{ZLine, ZOpcode}
+import millfork.assembly.z80._
 import millfork.node.ZRegister
 import ZOpcode._
 import ZRegister._
@@ -23,6 +23,29 @@ object LaterI80Optimizations {
     (Elidable & HasOpcode(CP) & Has8BitImmediate(0) & DoesntMatterWhatItDoesWithFlagsOtherThanSZ) ~~> { _ =>
       List(ZLine.register(OR, A))
     },
+    (Elidable & HasOpcode(CP) & Has8BitImmediate(1) & DoesntMatterWhatItDoesWithFlagsOtherThanSZ & DoesntMatterWhatItDoesWith(A)) ~~> { _ =>
+      List(ZLine.register(DEC, A))
+    },
+    (Elidable & HasOpcode(CP) & Has8BitImmediate(255) & DoesntMatterWhatItDoesWithFlagsOtherThanSZ & DoesntMatterWhatItDoesWith(A)) ~~> { _ =>
+      List(ZLine.register(INC, A))
+    },
+
+    (Elidable & HasOpcodeIn(Set(JP, JR)) & HasRegisters(IfFlagClear(ZFlag.C)) & MatchParameter(0)) ~
+      (Elidable & HasOpcode(INC) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~
+      (HasOpcode(LABEL) & MatchParameter(0)) ~~> (code => List(ZLine.imm8(ADC, 0), code.last)),
+
+    (Elidable & HasOpcodeIn(Set(JP, JR)) & HasRegisters(IfFlagSet(ZFlag.C)) & MatchParameter(0)) ~
+      (Elidable & HasOpcode(INC) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~
+      (HasOpcode(LABEL) & MatchParameter(0)) ~~> (code => List(ZLine.implied(CCF), ZLine.imm8(ADC, 0), code.last)),
+
+    (Elidable & HasOpcodeIn(Set(JP, JR)) & HasRegisters(IfFlagClear(ZFlag.C)) & MatchParameter(0)) ~
+      (Elidable & HasOpcode(DEC) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~
+      (HasOpcode(LABEL) & MatchParameter(0)) ~~> (code => List(ZLine.imm8(SBC, 0), code.last)),
+
+    (Elidable & HasOpcodeIn(Set(JP, JR)) & HasRegisters(IfFlagSet(ZFlag.C)) & MatchParameter(0)) ~
+      (Elidable & HasOpcode(DEC) & HasRegisterParam(A) & DoesntMatterWhatItDoesWithFlags) ~
+      (HasOpcode(LABEL) & MatchParameter(0)) ~~> (code => List(ZLine.implied(CCF), ZLine.imm8(SBC, 0), code.last)),
+
   )
 
   val FreeHL = new RuleBasedAssemblyOptimization("Free HL (later)",