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Z80: Fix line size calculations

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This commit is contained in:
Karol Stasiak 2018-07-31 00:52:01 +02:00
parent 2bac42c187
commit 53f550d266
2 changed files with 60 additions and 3 deletions
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9
src/main/scala/millfork/assembly/z80/ZLine.scala
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@ -175,7 +175,7 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
case BYTE => 1
case d if ZOpcodeClasses.NoopDiscards(d) => 0
case JP => registers match {
case OneRegister(HL | IX | IY) => 0
case OneRegister(HL | IX | IY) => 1
case _ => 2
}
case JR => 2
@ -185,11 +185,14 @@ case class ZLine(opcode: ZOpcode.Value, registers: ZRegisters, parameter: Consta
}
val fromParams = registers match {
case OneRegister(IX | IXL | IXH | IY | IYH | IYL | IMM_8) => 1
case OneRegister(MEM_IX_D | MEM_IY_D | IMM_16 | MEM_ABS_8 | MEM_ABS_16) => 2
case OneRegister(IMM_16 | MEM_ABS_8 | MEM_ABS_16) => 2
case OneRegisterOffset(MEM_IX_D | MEM_IY_D, _) => 2
case TwoRegisters(_, IX | IXL | IXH | IY | IYH | IYL | IMM_8) => 1
case TwoRegisters(_, MEM_IX_D | MEM_IY_D | IMM_16 | MEM_ABS_8 | MEM_ABS_16) => 2
case TwoRegistersOffset(_, MEM_IX_D | MEM_IY_D, _) => 2
case TwoRegisters(IX | IXL | IXH | IY | IYH | IYL | IMM_8, _) => 1
case TwoRegisters(MEM_IX_D | MEM_IY_D | IMM_16 | MEM_ABS_8 | MEM_ABS_16, _) => 2
case TwoRegisters(IMM_16 | MEM_ABS_8 | MEM_ABS_16, _) => 2
case TwoRegistersOffset(MEM_IX_D | MEM_IY_D, _, _) => 2
case _ => 0
}
inherent + fromParams

54
src/test/scala/millfork/test/ZLineSizeSuite.scala Normal file
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@ -0,0 +1,54 @@
package millfork.test
import millfork.{CompilationOptions, Cpu, CpuFamily}
import millfork.assembly.z80.{LocalVariableAddressViaIX, NoRegisters, ZLine}
import millfork.env.{Constant, Environment, NumericConstant}
import millfork.output.Z80Assembler
import millfork.test.emu._
import org.scalatest.{FunSuite, Matchers}
/**
* @author Karol Stasiak
*/
class ZLineSizeSuite extends FunSuite with Matchers {
private def runCase(line: ZLine): Unit = {
val platform = EmuPlatform.get(Cpu.Z80)
val env = new Environment(None, "", CpuFamily.I80, TestErrorReporting.log)
val options = CompilationOptions(platform, Map(), None, 0, TestErrorReporting.log)
val correctSize = new Z80Assembler(null, env, platform).emitInstruction("default", options, 0x100, line) - 0x100
val guessedSize = line.sizeInBytes
guessedSize should equal(correctSize)
}
test("Z80 instruction size") {
import millfork.assembly.z80.ZOpcode._
import millfork.node.ZRegister._
import millfork.env.Constant.Zero
runCase(ZLine.implied(RET))
runCase(ZLine.implied(NEG))
runCase(ZLine.implied(RETI))
runCase(ZLine.implied(RETN))
runCase(ZLine.implied(EX_DE_HL))
runCase(ZLine.implied(HALT))
runCase(ZLine.ldViaIx(0, A))
runCase(ZLine.ld8(B, C))
runCase(ZLine.ldImm8(B, 9))
runCase(ZLine.ldAbs8(A, Zero))
runCase(ZLine.ldAbs16(HL, Zero))
runCase(ZLine.ldImm16(HL, Zero))
runCase(ZLine.register(SLA, E))
runCase(ZLine.register(BIT0, E))
runCase(ZLine.register(JP, IX))
runCase(ZLine.register(JP, HL))
runCase(ZLine(IM, NoRegisters, NumericConstant(1, 1), true))
runCase(ZLine.register(DEC, HL))
runCase(ZLine.register(DEC, LocalVariableAddressViaIX(7)))
runCase(ZLine.ld8(A, MEM_HL))
runCase(ZLine.ld8(A, MEM_BC))
runCase(ZLine.ld8(A, MEM_DE))
runCase(ZLine.ld8(MEM_HL, A))
runCase(ZLine.ld8(MEM_BC, A))
runCase(ZLine.ld8(MEM_DE, A))
}
}